Sophisticated reliability checking, a unified rule deck and integrated debugging can go a long way to preventing device failures.
Electrical overstress (EOS) is one of the leading causes of IC failures across all semiconductor manufacturers, and is responsible for the vast majority of device failures and product returns. The use of multiple voltages increases the risk of EOS, so IC designers need to increase their diligence to ensure that thin-oxide digital transistors do not have direct or indirect paths to high-voltage portions of the design. With sophisticated reliability checking techniques, a unified rule deck, and integrated debugging environment, Calibre PERC helps designers eliminate the source of EOS failures without the use of manual markers or SPICE circuit simulation, while also enabling them to achieve the accurate and comprehensive verification necessary to ensure a repeatable and reliable design.
To download this white paper, click here.
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