Innovation In C-PHY

How the physical layer specification achieves higher data rates at low transition rate and lower power.


The addition of cameras and larger displays in mobile phones intensified the need to move data at higher speeds with fewer wires and low power using asymmetrical interfaces. The MIPI Alliance was formed in 2003 to standardize these interfaces and enable interoperability. The use of MIPI specifications has spread from mobile applications with extremely high-volume requirements to many other applications that use cameras and displays. The number of companies participating has grown dramatically since then. MIPI specifications are now deployed in mobile computing, automobiles, IoT devices, VR/AR/XR headsets, medical devices, among others.

To accommodate the fast-moving requirements, MIPI has updated many of their specifications. The original PHY specification, the D-PHY, uses the conventional approach of lanes with differential pairs for data and clock. Even though differential pairs use small voltage swings, the data rates for a 4 wire (2 data & 2 clock wires) connection could be improved upon.

Before Qualcomm joined MIPI, they developed the MDDI interface and made it available through VESA. After Qualcomm joined MIPI they proposed C-PHY as a new MIPI PHY technology. Is the C-PHY actually MDDI 2.0? We can only wonder!

C-PHY is revolutionary because it adds many innovations which allow it to offer higher data rates at low transition rate and lower power. This is achieved using a more complex transmitter, receiver, encoding, and mapping algorithms.

How did MIPI bring together several key innovations to achieve the impressive results shown by the C-PHY? The first was a move from using two wires as a differential pair transmitting one bit per symbol. Instead, C-PHY uses three wires; a trio, to send up to 2.28 bits per symbol. The D-PHY needs a second pair for the clock signal, which means there are really four wires per lane for the minimal configuration. The clever C-PHY encoding/decoding scheme allows the data lines to carry clock information, which ensures that each symbol has at least one transition on one of the three lines of the trio.

C-PHY uses three signal wires (A, B & C) with three possible levels for the signals. The algorithm imposes some rules to avoid the need for level detection of the three levels. The receiver generates 3 output bits, but they are not the values on the individual input lines. The receiver output bits are 1/0 values reflecting the differences between pairs in the trio. The first is True if A>B, the second if True if B>C and the third is True if C>A.

Added to this is the requirement that A, B and C must always be unique from each other, so no two share the same level at the same time. Out of all the possible combinations of three lines with 3 values, we have reduced the number of allowed combinations, or wire states, to 6.  From any of the 6 wire states there are 5 possible transitions to one of the remaining states.

All the allowed wire states of A, B & C have the same distribution of voltage signals, one each at around 0.125V, 0.25V and 0.375V, which minimizes common mode noise. The next technique is that the values of the three output lines are not the data, but rather states in a state machine. The transitions between the states have data values assigned to them. From any state in the FSM there is a legal transition to another state that corresponds to a data value from 0 to 4. So, you can see we are now working in base 5.

There are of course more possible combinations of values for the 3 lines, but those would introduce common mode noise, complicate the receiver design, and make the decoding impractical. The loss of values is easily compensated for by the removal of clock lines and the encoding that results in 2.28 bits per symbol. Using the transitions to indicate data means that no clock signal is required, the transitions themselves are the trigger.

So how much data can we transfer over this interface? Assuming we start with a 16-bit binary word size, we need to convert to base 5. We find that it will take 7 base-5 digits to carry a 16-bit binary value. The value of 216 is 65536.  We are using 57 which has the value of 78125, offering plenty of values to encode all the values used in a 16-bit word. Indeed, there are more values in the 7-digit base-5 word than we need for encoding data values. We are left with 12589 unmapped values.

How about the unmapped values? They can play an important role in the protocol because their values cannot be confused with any data stream values. Many of them are mapped to specific markers or control codes that are used to manage and control the protocol. Where does the 2.28 bits per symbol number come from? As shown above, we can transmit a 16-bit value with 7 base-5 symbols. This works out to 16 bits divided by 7 symbols, or 2.28 bits per symbol.

Let’s compare a 4 lane D-PHY with a 2 lane C-PHY implementation. The C-PHY will have a total of 6 wires, two trios. The D-PHY will have a clock pair and 4 data pairs, totaling 10 wires. Already we see we have 40% fewer wires. Let us compare a C-PHY running at 0.875 Gsps/Lane with a D-PHY supporting 1.0Gbps/Lane. Converting symbols to bits for the C-PHY and summing the lanes we arrive at 4.0Gbps per link on both C-PHY and D-PHY. However, the C-PHY uses fewer wires and has lower power consumption, both critical design objectives. With the smaller number of lanes required for C-PHY, even with more silicon area per lane, the overall C-PHY link has smaller area.

For systems that require higher data rates and can use C-PHY, it is a clear winner. Yet, there is a need for some chips to interface with both D-PHY or C-PHY. Because of the similarities at the signal level, it is possible to build PHYs that can operate in either mode. A one lane D-PHY connection with 4 wires can also support a single lane C-PHY link with a 3-wire trio. One wire simply goes unused or can even be shared with another C-PHY lane because there is no requirement for a paired clocking line in each lane. MIPI camera and display interfaces can interchangeably use C-PHY or D-PHY, which adds more reason to go with a combo C-PHY/D-PHY block.

Mixel was the first IP supplier to offer silicon proven C-PHY/D-PHY combo IP in 2016.  Since then, we have silicon proven the IP many different foundries and nodes to address the increased adoption of C-PHY.

The ability to support higher bandwidth with lower power, area and wires is increasingly becoming important in applications like automotive and AR/VR, where all these factors play an important role in product success. For instance, ADAS will often call for redundant imaging systems to ensure proper safety margins. The lower toggle rates for C-PHY can help simplify manufacturing and make a big difference where reducing costs is essential. As a result, C-PHY has seen widespread acceptance in many applications.


Ron Laugesen says:

Education article for an old timer.

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