Innovations Driving The Advanced Packaging Roadmap: Part Two

As the advanced packaging world enters the AI era, manufacturers are exploring ways to extend the life cycle of organic substrates and successfully introduce glass substrates to high volume manufacturing. In last month’s blog, “Innovations Driving The Advanced Packaging Roadmap: Part One,” we discussed the challenges of organic and glass substrates as the industry marches toward sub-2µm line/space (L/S) requirements (figure 1).

Fig. 1: The industry roadmap for the transition of substrates from organic (top) to glass (bottom) and the path to 1µm L/S. (Source: Onto Innovation)

Initially, it was thought that organic substrates would be unable to meet the new line/space requirements, prompting a hypothetical switch to glass substrates at the 2µm mark, but many in the industry are rethinking that assumption.

While glass substrates are poised to reach 1.5µm L/S, organic substrates will need a series of innovations to get there. We discussed these techniques in our previous blog. In this one, however, we will discuss an innovation glass substrates will need to reach sub-1.5µm L/S requirements. In order to improve the patterning of the build-up film dielectric vias – which will be needed – photo imageable dielectric (PID) materials could replace the laser drilled build-up film via process currently used in glass advanced IC substrates (AICS).

Let’s dive into that further.

Photo imageable dielectric

This proposed step would utilize either a dry film or a liquid PID to form vias and also possibly RDL trenches (damascene). Dry film PID, and some high viscosity liquid materials, are suitable for this process because they can planarize the surface topography, unlike many thin liquid PID materials which are conformal to the topography. The planarization effect of the dry film PID provides better electrical performance between the layers of RDL as they are separated by a dielectric of uniform thickness.

Another advantage for dry film PID: many customers already own lamination equipment, which can easily apply the material to both sides of the substrate. This removes the need to install large liquid slit/slot coating systems, providing manufacturers with a cost of ownership win.

However, using PID is not free of obstacles. The main challenge for PID involves aspect ratios, a similar obstacle faced by high aspect ratio photoresist imaging. Unlike the latter challenge, though, there is no reticle bias requirement for the lithography since copper seed is not flash etched. This allows a lithography system to print equal lines and spaces, making it easier to pattern images down to 1µm L/S. Once the patterns are aligned and defined, the copper seed layer is deposited over the entire panel. The panel is then plated uniformly, filling all of the vias and RDL structures. Afterward, chemical mechanical planarization (CMP) could be used to remove the excess copper, revealing the copper-filled PID structures. The success of high aspect ratio PID imaging will be key to the success of this process and will likely limit the extendibility of this process to smaller feature sizes.

Reaching roadmap milestones

The future AICS roadmap linewidth requirements are clear, but the path to success is not. There are many challenges along the way that need to be resolved. Only through collaboration will solutions be ready in time to match heterogeneous integration roadmap milestones.

To address these challenges, a full process line will be required, as many of the processes interact or are dependent upon one another. For example, the process biasing of reticles at less than 2µm L/S will be essential for plating processes requiring metal seed flash etch. Moreover, defect types and inspection sensitivity must be commensurate with the change in dimensions and processes to ensure HVM yield. Subtle equipment signal variations that can only be observed with AI models will need to be on hand to identify multivariable, high order effects not readily discernible through basic spreadsheets and regression analysis.

To foster such advanced packaging collaborations, Onto Innovation recently debuted the Packaging Applications Center of Excellence (PACE) at our Wilmington, Mass., headquarters. This panel R&D facility provides collaborators with access to Onto’s next generation tools for lithography, inspection and software process control. The collaboration also offers access to adjacent original equipment manufacturing equipment such as plating, laser drilling build-up films, TGV and PVD tools. In addition, the center gives collaborators access to the most advanced polymer chemistry for PID, photoresist and build-up films, which will be essential in reaching the 1µm L/S milestone by the end of the decade.

Through collaborations such as this, and others, the semiconductor industry will continue to see new innovations and shared successes involving advanced IC substrates, panel-level packaging and more. We at Onto Innovation look forward to working with our collaborators and customers to make this happen.