Innovative Integration Solutions For SiP Packages Using Fan-Out Wafer Level eWLB Technology

Fan-Out Wafer Level Packaging (FOWLP) has been established as one of the most versatile packaging technologies in the recent past and already accounts for a market value of over 1 billion USD due to its unique advantages. The technology combines high performance, increased functionality with a high potential for heterogeneous integration and reduced overall form factor as well as cost effectiveness. The increasing complexities in achieving a higher degree of performance, bandwidth and better power efficiency in various markets are pushing the boundaries of emerging packaging technologies to smaller form factor packaging designs with finer line/width spacing as well as improved thermal/electrical performance and the integration of System-in-Package (SiP) or 3D capabilities.

SiP technology has been evolving through utilization of various package technology building blocks to serve the market needs with respect to miniaturization, higher integration, and smaller form factor as cited above, with the added benefits of lower cost and faster time to market as compared to silicon (Si) level integration, which is commonly called system- on-chip or SoC. As such, SiP incorporates flip chip (FC), wire bond (WB), and fan-out wafer- level packaging (FOWLP) as its technology building blocks and serves various end applications ranging from radio frequency (RF), power amplifiers (PA), Micro-Electro- Mechanical-Systems (MEMS) and Sensors, and connectivity, to more advanced application processors (AP), and other logic devices such as graphics processing units (GPUs)/central processing units (CPUs). FOWLP, also referred to as advanced embedded Wafer Level Ball Grid Array (eWLB) technology, provides a versatile platform for the semiconductor industry’s technology evolution from single or multi-die 2D package designs to 2.5D interposers and 3D SiP configurations.

This paper presents developments in SiP applications with eWLB/Fan-out WLP technology, integration of various functional blocks such as wire bonding, Package-on- Package (PoP), 2.5D, 3D, smaller form factor, embedded passives, multiple redistribution layer routing and z-height reduction. To read more, click here.