Innovative Wafers For Energy-Efficient CMOS Technology

Innovative wafers for energy-efficient CMOS technology


For continued attractiveness and competitiveness of advanced electronic appliances such as smartphones, TVs, notebooks or tablets, the semiconductor industry is moving to “fully depleted” transistor technology to build integrated circuits. This technology comes in two flavors: planar and tri-dimensional (FinFET), each with its own advantages and challenges. This White Paper explains how innovative wafers, which are the foundations of silicon chips, will play a role to enable or facilitate the introduction of the planar and non-planar approaches to fully depleted technology, starting at the 28nm node. It also outlines the benefits that users can expect.

To view this white paper, click here.

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