Interaction Of Hard IP And Chip-Package

Current and future customer-specific circuit development requires an increasing number of different interfaces, such as for memory (DDR3, DDR4, LPDDR3, LPDDR4, etc.), radio interfaces (Bluetooth, NBIoT, etc.) or high-speed LVDS/SERDES interfaces (DisplayPort, Ethernet, USB, etc.). For customer-specific circuit projects, these components are frequently purchased as hard IP because the development would require too much effort in terms of manpower and therefore be too expensive for individual projects.

Furthermore, such design projects frequently also require new packaging technologies with a very challenging chip-package interface consisting of copper pillars or micro bumps. For newer technologies, the spacing between these structures is being reduced further in order to realize the required number of connections between the chip and the package.

However, the copper pillars or micro bumps are used here for very different functions. For instance, they must ensure the power supply to the circuit, even at different voltage levels. In addition, the high-frequency signals for the radio interfaces, signals for the high-speed interfaces and many other signals must be realized.

For this reason, finding the correct arrangement is very challenging and is further complicated by the use of hard IP. On one hand, it is frequently desired that no additional copper pillars or micro bumps be placed above the hard IP. This wish is motivated by the fact that the electrical utilization and thereby the influence on the hard IP cannot be verified for these structures. On the other hand, the corresponding copper pillars or micro bumps needed by the hard IP for all signals and power supplies must be placed on the IP in order that it can be used as simply as possible in the design. If this is successful, the hard IP can be verified very well already in advance.

However, it is increasingly common to encounter conflicting goals between the hard IP area and the area that is needed for the copper pillars or micro bumps. Because the circuit area for the hard IP is determined by the design and the technology, only the area for the pillars or bumps can be modified. The spacing between the corresponding structures is the factor that can be influenced here. This can sometimes result in very small spacings. Because many different hard IPs are integrated into a circuit, however, this approach has the disadvantage that the hard IP with the lowest spacing defines the manufacturing technology for all copper pillars or micro bumps. In turn, this also influences the costs for their manufacturing and the manufacturing of the corresponding package substrate. As a result, a hard IP can dramatically impact the total costs of the circuit.

For this reason, it will be necessary in the future to develop new strategies for the integration of copper pillars or micro bumps into the hard IP. For example, it will then be possible to designate corresponding areas where such structures may be placed on the hard IP or even corresponding lock-out areas, where it is defined that no structures may be present. The development of standards will be critical here in order to ensure uniform practices. The placement of the copper pillars or micro bumps must then be realized on the top level using appropriate tools that are capable of taking into account the various conditions and requirements.