IoT Brings Low Power To Forefront

Low power has become a primary design consideration over the past decade, driven by consumer portable devices packing in greater amounts of processing power and sophisticated communications, while at the same time providing extended battery life even though developments in battery technology have advanced little in the same timeframe. But the (IoT) will take those requirements to new heights and spread them to additional parts of the design flow.

This could create some interesting challenges and opportunities for the EDA industry. Almost since the dawn of EDA, the two primary design considerations have been timing and area. While area remains important, timing is dropping in importance. “Low power is going to be the key design success metric,” says Aveek Sarkar, vice president for ANSYS/Apache. “For these designs, it is going to be less about timing or other traditional design concerns and more about how to reduce the switching and leakage power without compromising area and performance.”

While we talk about power as having become a primary attribute for optimization, it is still not front and center in most tools. “This is not about squeezing power out of a block by algorithmic methods,” says , a Cadence fellow, “but what insights can I give to an architecture and software team about what is going on in each of the 14 interesting scenarios so they are more in control. Architects make some crude stabs at the problem early in the process and then pray.”

Others agree that this is where the power optimization has to start. “The optimization for energy efficient operation of mobile devices starts with the architectural design phase,” says Johannes Stahl, director of product marketing for virtual prototyping at Synopsys. “At this level the fundamental decisions are taken about how to jointly optimize the architecture and power management strategy for the execution of the key use cases.”

Adds Bernard Murphy, chief technology officer for Atrenta: “You have to start with meaningful power estimates, otherwise improvements are irrelevant. At the TLM-level, getting estimates that correspond in any way to the implemented design is not easy. This can work if you are developing something quite close to a previous design from which you can interpolate models, but it is completely hopeless for new designs or significantly changed designs.”

The IoT does not always create specific demands. “So far we have not had any specific requests related to the IoT,” says Anand Iyer, director of product marketing for Calypto. “What we do see are many people wanting to take existing IP blocks and to add more advanced power optimization capabilities to it, such as clock or power gating. We are also seeing a trend that our customers are increasingly moving to higher levels of abstraction such as C/C++ from RTL. By moving to higher abstraction levels, designers are able to explore multiple microarchitecture scenarios.”

Sarkar provides an example of the power reduction potential. One of their clients used RTL power analysis to reduce the power consumption of the digital parts of the design by 82% for a 180nm design without changing their area usage. This brought about a reduction from 44uW to 7uW.

But this is all about power optimization for the digital content in consumer devices, and the IoT is somewhat different. No longer does the digital circuitry dominate the design. Analog is becoming more important and consuming a significant portion of the chip area and power budget. “Based on process technology, the digital portion of IoT device power consumption and silicon footprint is getting insignificant,” says Hem Hingarh, vice president of engineering for Synapse Design. “Depending on the end application, the analog portion of an IoT device is likely to be a greater percentage of the total area and power consumption compared to the mainstream devices today, especially when the IoT device requires RF interfaces such as Bluetooth, GPS, WiFi, and mobile connectivity with 3G and 4G-LTE.”

Sivan Nagireddi, a senior principal engineer at Synapse Design, puts a number on it: “Based on various physical wireless network connections, the RF and analog section power dissipation far exceeds 75% of the total power budget.”

Because of this, power optimization for analog will become equally important and several techniques are in use today. Sarkar identifies two extensions from the digital side that equally apply in the analog domain. “We are seeing power gates going into PLLs and other circuits which have not had these in the past. Another change is the increased usage of on-chip power regulator.”

Krishna Balachandran, product marketing director for low power at Cadence, explains some of the techniques that are being used in the analog domain today. “You are always trading off performance or resolution against power. There is no free lunch. design is becoming increasingly popular because this can be used to help reduce power. In most cases the same function can be performed in digital for a smaller area than would have been consumed by the analog. The other way is to use the digital logic to assist the analog, adding capabilities such as tuning, compensation etc.”

Power gating is also possible for the analog portions. “It can be tricky to deal with issues such as stability and the time necessary to reach a quiescent state,” says Balachandran. “It has to be done more carefully than for digital design.”

Another area of interest is near-threshold and sub-threshold computing, which is a tradeoff against performance. “This may be acceptable for IoT applications where performance may not be the primary design criteria,” explains Balachandran. “The power savings can be up to 10X but may also cause a 10X reduction in performance. If you only need to operate at a few megahertz, this may be a good tradeoff.”

Analog does not scale well as you go to smaller nodes, but this is somewhat of a silver lining for the IoT because the larger nodes tend to be a lot cheaper to manufacture and as a bonus, leakage is better at larger nodes. 180nm leaks a lot less than 65nm. “Leakage is important in analog but it can be controlled more by modifying the operating points of the devices,” says Balachandran. “The smaller nodes also prohibit the use of body biasing.”

Migrating from the lower levels to the very top, additional efforts will be necessary to properly tie the software into any power options that are provided. “Relatively little has been done to create the software environment and the methodologies that allow the software team to know when to turn things on and off,” Says Rowen. “We have created the potential but the systematic optimization of it is at a primitive level. This means that power is being kept on too much of the time for many of the blocks.”

Stahl adds that “the software and hardware teams spend a lot of time in writing and reading specifications, but in many cases fail to exploit the features efficiently or even correctly.”

The integration of analog, digital and software creates a number of problems in the EDA tool flow. Jeff Berkman, senior director of IC development at Echelon uses many of the techniques talked about in this article. He notes that “the biggest problem with digital / analog integration is cross training. They talk different languages. There are completely different methodologies used by the two teams.”

A top-down design flow also relies on models being available. Berkman again points to some difficulties. “We do not use analog abstractions. The modeling effort is large. We believe that it was faster for us to design it, run a shuttle for the analog pieces and test it in real life. This enables us to get the front-end back, and to run our impairment tests that may take a week.”

“Mixed-signal design and verification will likely get a boost from the IoT,” says Balachandran. “There will be increasing digital content that is closely coupled with the analog content and there will be many signal crossings between the domains and this has to be carefully verified and assembled.”