IP Design Essentials For Power Integrity

Smart connectivity is the new mantra of today – the ability to connect to anything, anywhere and at any time. With such technology enablement, low power is not a choice but an expectation. Whether it is a connected device, or a system that is part of the infrastructure, they are driven to integrate various functionality such as high speed computing, high-speed memory, memory interfaces, radio, Bluetooth, WiFi, etc., onto one System-on-a-Chip (SoC) to significantly reduce area, form factor, cost and power.

The lowering of power is required not only for the mobile applications which strive for battery life, but also for other applications like SoCs used in data centers where energy efficiency is a key factor to control the overall operational costs. Moore’s Law based process scaling has enabled integration of a variety of IPs in today’s SoCs, allowing them to meet the market demands, delivering higher performance while consuming lower power.

IP providers are in the forefront of SoC development process, engaging with major customers and foundries well in advance to make sure that the IPs are ready even before SoC designers start to design with them. For advanced technology nodes, this becomes a collaborative development process between the IP developer, foundry partner, customer and EDA partner. It evolves with the PDK development, including the changes to RC extraction, EM rules, inclusion of new parasitic/device caps etc., all the way until the process technology matures.

What complicates this situation even further is the fact that IP designs are targeted for a wide variety of applications and technology/process nodes. As voltages fall and the current density increases with process advancement, noise margins are greatly reduced, making the designs very sensitive to power supply noise. For instance, if 100mV noise in 1V supply for 28nm technology wasn’t bad enough, imagine the impact of a 100mV noise in 0.7V supply for 16nm and below. This is reason enough to emphasize the importance of power delivery network design within the IP and the critical role it plays in achieving the desired functionality of the IP under different usage scenarios. Hence power integrity is a key sign off metric and it is imperative to use a design methodology that help address power noise issues from early in the design to final sign off.

Traditional SPICE-based simulation for power noise analysis suffers from several drawbacks, such as the need for a clean LVS and post extracted layout netlist, which is only available much later in the design cycle. As a result, the verification time is reduced to a small window. Designers spend extensive amount of time in the iterative exercise of cleaning up their design for LVS issues and performing RC extraction before even running any sort of simulation to detect IR drop issues. In addition, debugging IR drop issues using a netlist-only based approach is ineffective. What is needed is a more streamlined methodology that allows designers to continuously improve power integrity by using data that evolves over the design process cycle.

Early Grid Weakness Analysis: The first thing in the verification of power integrity is the availability of a physical database, and for analog, custom digital and AMS designs, it is the GDS. Using the GDS, the methodology should allow for early PG grid weakness checks and visual inspection of the results. PG weakness checks will reveal the relative strengths and weaknesses of transistors connected to the power and ground pads in the design. This allows a layout designer to easily determine where the routing needs to be improved for a robust power grid, without relying on a netlist, LVS verification, power target or designer intervention.

Static IR Drop Analysis: The IR drop analysis allows a designer to assign power targets and analyze the integrity of the grid based on average power consumption. Because IPs can be used in a variety of applications, coverage is key. The methodology should allow region-based power assignment to detect IR drop issues for different usage scenarios. The ability to visually inspect grid connectivity bottlenecks and transistor current distribution enable quick root causing of any IR drop issues in the design. The increase in functional integration and the drive for low power adds design complexity in the form of multiple supply voltage domains, power gating schemes, etc. Hence the ability to concurrently analyze multiple voltage domains and to automatically identify and characterize power switches in the design becomes critical.

Dynamic Voltage Drop (DvD) Analysis: Next in a streamlined flow is the dynamic voltage drop analysis, where transistor currents are characterized and a true transient simulation is performed to capture realistic switching scenarios. Because running an exhaustive transient simulation for power noise analysis can be time consuming, the methodology should promote the ability to analyze just the required states of IP operations, as well as simulating these multiple states in a single DvD run. Modeling different device decaps and running hot spot analysis and plotting region based currents to understand the impact of simultaneous switching on the local and global grid makes the design verification and debug a lot more effective. The methodology should allow designers to add or delete metal straps, vias, pads, etc., on the fly and perform what-if analysis including incremental extraction for faster convergence.

Substrate Noise Analysis: An important aspect in the realm of AMS designs is the impact of integrating noisy digital circuitry and the sensitive analog circuitry on the same substrate. For accurate power noise analysis it is important for a designer to model the propagation of substrate noise in DvD analysis. IP designers have no visibility into how their IPs will be integrated at the SoC level. If AMS and analog IPs are integrated close to high-speed digital circuitry on an SoC, they will suffer from switching noise propagated through the substrate, especially if sufficient isolation is not guaranteed at the IP level.

For reliable operation of an IP at the SoC level, it is critical to have a methodology that allows modeling of the substrate noise generated in a typical SoC environment using digital noise injection, and perform analysis to determine the frequency and time-domain response of an IP. It is important to adopt the right isolation techniques for a specific technology node by planning the isolation structures such as p-guard ring, deep nwell tub, deep nwell guard ring etc. early in the design cycle using test structures.

The journey of a thousand miles begins with the first step and the road to silicon success of an IP begins with the choice of design methodology for verification and sign off. Changing market needs, design trends and the requirements for increased functionality with higher performance and lower power are all driving the need for a smart power analysis solution that can address connectivity checks, IR drop, DvD and substrate noise analysis from early in the design cycle all the way to sign off. With change being the only constant that IP developers are striving against, a systematic power analysis methodology is key to ensuring the functionality of the IP in a wide variety of applications.