IP Market Booms At Advanced Nodes

Market conditions and business pressures are creating new opportunities for IP subsystem integrators.

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As SoC design and manufacturing costs rise, system OEMs are wringing as much of that increase as they can from ASIC vendors. The result is that engineering teams on the design and test side are being constrained by budgets at a time when complexity is rising and time-to-market pressures are increasing.

At least one segment is benefiting from directly this. Budgetary limits are forcing chipmakers to rely increasingly on commercial Intellectual Property and IP subsystems, and this trend is becoming more at advanced nodes where complexity is higher than at any previous nodes.

“We have seen a 3X increase in the number of IP suppliers at 28nm vs. 65nm, for example,” said Patrick Soheili, vice president of product management and corporate development at eSilicon. “Today, it is typical to have at least 10 IP suppliers involved in a leading-edge design. Each of these suppliers might provide 2 to 3 IPs each, so the number is growing rapidly. Advanced technology demands a narrowly focused design to meet power and speed requirements, and that is contributing to the rise in the number if IPs per design. The proliferation of standards is also driving this. This IP proliferation drives a roll-up of IPs into macro building blocks, creating more IP subsystems. ‘One size fits all’ just doesn’t work anymore.”

As a result of the pressures on engineering teams, IP vendors such as Synopsys are seeing a rise in IP integration services requested by customers, as well, especially in the area of IP subsystems.

Navraj Nandra, senior director of marketing for the DesignWare Analog and MSIP Solutions Group at Synopsys, noted that during a recent meeting to review a project in which the customer’s chip has just come back [from the fab], he and his team found their IP subsystem worked a lot better and the process was a lot easier than a previous engagement where there were disparate pieces of IP and the customer went through the pain of figuring out how to integrate them. “This time we actually delivered them the complete IP subsystem for USB 3.0. The customer saw all the value of working with an external IP vendor, the lower cost of ownership, but this time around we took it one step further and we integrated the complete USB protocol with the PHY, the controller, the digital piece and the firmware.”

Nandra noted that the SoC floorplan was unique to the customer. “The way and where and how the IP is placed is going to be different for each customer. I don’t imagine that we would be able to re-use the IP subsystem exactly as it exists with another customer. We would have to re-do the individual block integration for the next customer. But what it does show the next customer is that we’ve done this one, and we are capable of absorbing the customer’s environment as we integrate our IPs into their chips.”

He noted that it is also possible to do some power exploration at that subsystem level. “Not only is it the low level analog/mixed-signal blocks, but you’ve got the ability now to do power exploration at the subsystem level.”

Prasad Subramaniam, vice president of design technology at eSilicon, is seeing a rise in front-end design services in general, not just for IP subsystems. “It’s usually around I/O interfaces or processor subsystems. Customers don’t want a collection of IP. They want full solutions so they can focus their engineering on differentiation. We see lots of SerDes and controller integration. This can be complex, as there is a gray area between what functionality is in the SerDes and controller blocks, especially when multiple suppliers are involved.”

Hem Hingarh, vice president of engineering at Synapse Design, agreed there is a strong uptick in demand of IP integration services. “With technology scaling, our customers are developing their SoCs for multiple marketing reasons—functionality, cost reduction and low power. All customers want to integrate more and more functionalities on a chip. We see cases of reduced overall system BOM integrating some of the old chips into a single chip. And of course lower power is becoming one of the most critical requirements for all SOCs regardless of process technology.”

IP is not new, the ecosystem is
Samuel George, director design enablement at GlobalFoundries, said IP use has been increasing for the last 12 years. “Now more and more SoCs are relying on third-party suppliers to provide IP, which came from the beginnings of interface standards and the ability to actually have specifications for interface and foundation IP blocks that meet a lot of the SoC needs. With that there’s been more and more occurring there. There’s obviously been the ability to bring in this IP. But more than that, we’ve been hit with increased costs for SoCs and ASICs. That movement has just accelerated.”

With those increased costs, fabless semiconductor companies are looking to get IP from sources where the cost can be amortized across multiple parties, he explained. “In doing that, the IP interfaces have gotten more and more complicated, which brings you to why there’s more and more integration services. You see high speed SerDes now, but depending on the application it’s no longer just going up to 2, 3 or 6 Gbps SerDes. It’s commonplace right now for PCIe 3 and USB 3 that requires 10 to 12.5 Gbps SerDes. With PCIe 4.0, that’s now going up to 16, and that doesn’t get us into the communications and storage standards. Networking standards are starting to get up to 28 and 30 Gbps and beyond.”

“With those kinds of interfaces, as well as the cost aspects, getting IP from the outside is what’s leading to a growing need for integration services. In the end, you want to make sure the SoC works and you don’t want to have a situation where a piece of IP is the reason that silicon doesn’t work,” he continued. “If you go back to the costs and trends that are taking place, even a few years ago there were still very large companies doing their own IP. Even with guys that you figured would never completely go outside, you’re seeing some shifts. You go down the list and say, ‘Who’s left?’ There is more and more of a push to not bear the brunt of producing IP internally.”

GlobalFoundries itself does not have its own design services arm, but it does work with with partners in its ecosystem. “We’re not in the design services business,” George stressed. Also, the company announced a relationship with Invecas in November — an independent company that has an exclusive arrangement with GlobalFoundries similar to the relationship between Global Unichip and TSMC. The benefit is that Invecas can optimize just for GlobalFoundries’ process rather than try to produce things across processes.

When it comes to the integration of the subsystem into the chip, Drew Wingard, CTO of Sonics pointed out that there are interesting sets of applications that are pushing the performance curve or the power curve in such an aggressive fashion that customized solutions are always going to be more attractive. But he doesn’t believe this is the main part of the market at this point. “I suspect that for the main part of the market, with the exception of a very small number of domains, the design of general purpose subsystems is still relatively new. What we’re finding is that a company that thinks of itself as a subsystem provider may not have not gotten a sufficiently flexible definition of their subsystem so they can actually articulate that as a product.”

To Hans Bouwmeester, vice president of engineering operations at Open-Silicon, it appears that subsystems are being more talked about than before. “Of course, the whole concept of an IP subsystem is not new. It is, in that sense not rocket science. It’s not a an invention or anything. It’s about moving to the next abstraction level. But definitely, over the past months or year, there seems to be some true movement rather than just talk. As you look at modern SoCs and ASICs, there are very often dozens of different types of IPs on the chip, and these IPs often come from different vendors. All these IPs, of course, need to interoperate with each other. When it comes to the interoperation, there are so many aspects. There are physical aspects when it comes to, for example, making sure that the IP is compatible with each other for the metal stack or other physical types of requirements such as process technology options from the fab. There is electrical interoperability, logical/functional interoperability, packaging and test aspects that need to be interoperability-proven between IPs. It starts to make sense to see the IP more as a bundle of IPs where the vendor takes more of that responsibility.”

That is especially true if the IP is not something that is highly differentiated.

From an ASIC perspective, Bowmeester said other changes are afoot. “In the ASIC world in the past it used to be the case that our customer would do the front-end design — meaning, they would take care of the RTL — and then they would hand over the RTL to their ASIC partner. The ASIC partner, whether it be an Open-Silicon or an Avago or a VeriSilicon, would take care of the physical design, the test integration, the packaging, the qualification, the characterization and ultimately running the production, selling good parts back to the customer. It was really a hand-off where the customer did the front end and the ASIC vendor did the back end. Now the change we are starting to see more and more is that ASIC customers are looking to their vendor to take care of the more horizontal aspect, where they would then take care of the more vertical aspects.”

This is definitely in line with the rise in IP subsystem integration services in that the customer is basically looking to outsource what does not add differentiation, and are looking to do in-house what does add differentiation, Bouwmeester added.

That goes for software as well as hardware. “A lot of the software is no longer differentiating to customers. It becomes more of a horizontal type of component. If you think of boot code or firmware drivers or interrupt service routines, customers more and more are willing to outsource, and would prefer to outsource that to third parties. In that context, it then starts making sense to offer a subsystem solution that is not only the hardware, but also software, which are part of what ultimately what runs the IP, whether it’s an audio subsystem or a video subsystem or an encryption subsystem,” he added.

Nandra sees a bigger market for all of this. “Why should a customer worry about all of that stuff when at the end of the day they’re getting all of those pieces from the IP vendor, so they should get that service too. The IP market is evolving with more competition, which is driving new business strategies for success.”