Leverage Functional Interfaces For High-Speed Test Access During All Phases Of The Silicon Lifecycle

Chip testing used to be straightforward. The development team used fault simulation to select a subset of the functional tests that could detect most possible manufacturing faults. These were translated to test patterns that ran on automated test equipment (ATE) to screen out defective dies at wafer test and bad packaged chips in final test. Lots of new technology was introduced over time, including scan and other design-for-test (DFT) integrated with synthesis, automatic test pattern generation (ATPG), built-in self-test (BIST), and the IEEE 1149 JTAG boundary scan standard. But one aspect of chip test remained constant: the test patterns or scan data were applied using interfaces such as general-purpose input/output (GPIO) that run much slower than the buses used for functional (mission) purposes. Consuming a large number of GPIO pins was not regarded as a problem.

This has changed with recent generations of system-on-chip (SoC) devices. Increased design size and complexity, fewer GPIO pins relative to the number of scan chains, advanced technology nodes with high transistor density, manufacturing variability, and 2.5D/3D packaging all complicate chip test. The number of test patterns required has grown from a few thousand to a few hundred thousand, making test time prohibitive on expensive ATE. In parallel, the very definition of chip test has expanded beyond manufacturing into the field. Aging effects and silicon degradation over time, especially in safety-critical applications, must be detected for chips in active use in end products. The combination of these factors demands a new solution that runs tests much faster at multiple points in the silicon lifecycle, from post-silicon validation (PSV) of prototypes in the bring-up lab through chip manufacturing test using ATE, system-level test (SLT) of the assembled board containing the chip, and in system test (IST) of the assembled product in the field.

Of course, modern SoCs have high-speed, high-bandwidth interfaces available for functional purposes. For example, the sixth generation of the popular PCI Express (PCIe) standard is rated at 64 gigatransfers per second. The fourth generation of the ubiquitous Universal Serial Bus (USB) clocks at 40 gigabits per second. Both are much faster than traditional interfaces for ATE data transfer. One solution to the increasing demand for faster test is to leverage the high-speed I/O (HSIO) interfaces that already exist. When a chip is being tested, it is not actively communicating with other chips. Using its functional interfaces as part of the testing process is a logical and very effective approach. To satisfy the requirement of unified testing across the full silicon lifecycle, the testing must be flexible as well as fast.

Using functional HSIO to perform high-bandwidth test is made much easier with Synopsys Silicon Lifecycle Management (SLM) High-Speed Access & Test (HSAT) IP. Designers can instantiate this IP into their SoCs to seamlessly connect chip DFT infrastructure to interfaces such as PCIe, USB, Serial Peripheral Interface (SPI), Mobile Industry Processor Interface (MIPI), and IEEE 1149.10. This is much faster than using GPIO for test and it avoids having to allocate GPIO pins for test purposes. In fact, no additional pins are required at all. The connection to the HSIO interface is made using a configurable Arm AXI bus and a FIFO suitable for the design’s DFT approach. A bypass mode to use GPIO pins is available. The connection to the DFT logic is flexible to accommodate different approaches, including configurable scan chain, compression, and JTAG Test Access Port (TAP) support. These capabilities provide maximum interoperability across many different types of SoCs.

HSAT IP is combined with Synopsys Test Adaptive Learning Engine (ALE) software to reuse standard HSIOs to get test, debug, and monitoring data in and out of an SoC at gigabit data rates. ALE leverages HSAT IP to accommodate a wide variety of standard high-speed interfaces. It automatically packetizes and depacketizes scan data for transmission over the interface. It reads in Standard Test Interface Language (STIL) from TestMAX ATPG and generates failure log files for debug purposes. ALE provides the software interface to the HSIO similar to a device driver, enabling communication between the operating system file I/O and the software layer driving the host HSIO. The same flow works for ATE, SLT, and IST. Repeating manufacturing tests in the field provide early visibility into functional or performance degradation over the chip’s lifetime. This solution can also be used to access data from SLM monitors, including:

• Environmental: power, voltage temperature (PVT)
• Structural: path margin (PM)
• Functional: bus, clock, processor workload, and interface eye diagram at high speed

ALE includes an adaptive learning engine to perform volume data analysis and support efficient and high-quality testing. In manufacturing, this engine leverages the data gathered from multiple ATE testers and multiple die/wafer lots for adaptive testing. In the field, data harvested from chips deployed in a range of applications and environments can help identify trends in aging and degradation, enabling failure prediction and preventive action before systems actually fail. The resulting level of test quality and runtime reliability metrics meets the needs of the most demanding safety-critical applications and their related standards, such as ISO 26262 for automobiles and other road vehicles.

In summary, chip test is undergoing major changes in the manufacturing process and expanding into new domains. Traditional methods using low-speed interfaces take too long to run tests and require dedicated pins, both adding to chip cost, and are not extensible. The Synopsys solution with HSAT IP and ALE tool leverages existing functional HSIO such as PCIe and USB to speed up SoC test while adding no pins. The solution scales as new generations of HSIO standards are defined. High-bandwidth testing is possible from wafer test to in-field monitoring, spanning the entire silicon lifecycle. Fast, low-cost, flexible, and scalable chip test is now available for all development and ATE teams.

For more information, visit https://www.synopsys.com/solutions/silicon-lifecycle-management/high-speed-access-and-test.html and https://www.synopsys.com/implementation-and-signoff/test-automation/testmax-ale.html.