How the increase in interconnect communication speed introduces challenges such as signal integrity, crosstalk, and power consumption, each of which must be addressed to help ensure design feasibility and cost effectiveness before manufacturing.
The exploding demand for more data driven by advancements such as artificial intelligence and machine learning has created an increase in bandwidth (BW) for interconnects for different systems and hardware components such as graphic cards, network cards, storge devices, CPUs, memories, and many more. PCIe is the leading high-speed serial communication protocol for connecting such hardware components. The PCI Special Interest Group (PCI-SIG) has defined the PCIe 6.0 specification and is defining the upcoming PCIe 7.0 specification to address this explosion of data by increasing the bandwidth (BW) of the communication to 64Gbps and 128Gbps Pulse Amplitude Modulation 4-level (PAM4) correspondingly. This whitepaper discusses how the increase in interconnect communication speed introduces challenges such as signal integrity, crosstalk, and power consumption, each of which must be addressed to help ensure design feasibility and cost effectiveness before manufacturing. Such challenges can be analyzed and addressed in a more efficient format using the IBIS-AMI (Input/Output Buffer Information Specification-Algorithmic Model Interface) approach.
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