Limits For TSVs In 3D Stacks?

By Ed Sperling
Semiconductor design always has been about solving technology issues one node at a time, often in the face of a perpetual barrage of looming problems. In fact, if there is any change at all, it’s in the number of threats that have to be solved now at each node, most of them driven by ever-increasing density and the laws of physics.

Stacking die holds the promise of becoming something of a game changer because it can solve multiple issues at once—power, performance, physical effects such as noise and crosstalk—while creating its own issues such as who’s responsible when two known good die don’t work in a package.

But the surprise among companies working with this packaging approach is that it’s harder to remove the heat from stacked die than anyone initially thought. The generally accepted premise that silicon is a good conductor of heat is true, but apparently not true enough. Early tests show that 3D stacks are showing some limits for through-silicon vias.

“What we found is that you have about a 7 to 10 watt maximum for through-silicon vias using current technology,” said Greg Bartlett, senior vice president of technology and integration engineering at GlobalFoundries. “After that you have to go to an interposer.”

This is somewhat counterintuitive, because most engineers have always assumed that 3D stacking would be the successor to 2.5D stacks. Unless something is done to change the technology, it may be the other way around. This is good news in one sense. It’s cheaper and easier to work with an interposer, which contains TSVs on a separate piece of silicon, than with TSVs running directly through stacked layers of thinner chips. There is less stress to deal with from drilling through a layer of silicon, and yield is higher if those TSVs are run through a thicker piece of silicon.

“The big problem now is that with a dense TSV the heat is trapped,” said Dian Yang, senior vice president of product management at Apache. “You have to use metal to dissipate the heat. People didn’t know the power density would be so high, and that has causes thermal issues that are much more severe.”

In 2.5D stacking, the tradeoff is the footprint. A 3D stack is much smaller and can fit into smaller spaces, which is why it has been of particular interest to companies such as Broadcom and Qualcomm.

It’s not the TSV technology itself that is causing problems. It’s the location of the TSVs. There are still places where TSVs work extremely well, such as inside of interposers and in stacked memory configurations. Memory is particularly attractive because it doesn’t generate heat anywhere near the level of logic. Micron and Samsung are both developing stacked memory configurations using TSVs and claim faster performance, higher density and lower power. This kind of memory can be used in a 2.5D as well as a 3D stack.

Other considerations are under way, as well, such as using different substrate materials using different cooling methods, such as microfluidics. But there will either have to be a compelling technology reason, which so far has not been proven, or a major ability to reduce the cost of these approaches before this kind of technology hits the mainstream. Until then, it’s anyone’s guess whether and for how long a pure 3D stacking approach will be successful.