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Machine Learning-Driven Full-Flow Chip Design Automation

Engineering teams can to become more productive using a reinforcement learning engine to meet the challenges of large and more complex system-on-chip (SoC) designs.

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To enable the semiconductor industry to continue growing, the chip design process must become more efficient. With the availability of massive, cloud-enabled, distributed computing and advancements in machine learning computer science, the next chip design automation revolution is now possible. The Cadence® Cerebrus™ Intelligent Chip Explorer utilizes both of these technologies, based on the industry-leading Cadence digital full flow, to deliver better power, performance, and area (PPA) more quickly. Engineering teams now are able to scale and become more productive using the Cadence Cerebrus reinforcement learning engine to meet the challenges of increasingly large and more complex system-on-chip (SoC) designs.

By Rod Metcalfe, ML Product Manager, Cadence

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