Making Connections

By Ed Sperling

The world is still full of engineers who can build fast interconnects to things like PCI Express or USB 2.0 who can create complex schematics for determining the connections between a processor core, memory, logic and various IP blocks on a piece of silicon. But over the next several years, many of those engineers will have to figure out new ways to make a living.

The number of companies that are jumping into pre-configured interconnect strategies—either through existing bus structures such as AMBA or the emerging network on chip approach—is growing rapidly. This is the latest trend in the disaggregation of the supply chain for systems on chip, using pre-configured approaches or high-level flexibility to plug in third-part components instead of developing everything in-house.

There are several reasons these approaches are gaining in popularity:

1. Complexity is making it harder to keep track of the interconnects, particularly in devices where there are multiple cores and multiple power islands that can be turned on and off.
2. Smaller staffs with targeted resources, or even the same size staff with more complex demands, are forcing design teams to put their resources where they can make a competitive difference rather than re-inventing something that is good enough and which adds no value.
3. Market windows are forcing companies to rethink their make vs. buy decisions, which is driving decisions about everything from intellectual property to restrictive layouts.

Riding the bus

One of the earliest standardized approaches to solving interconnects was the bus approach, and it remains popular in many chip designs today. ARM rolled out the Advanced Microcontroller Bus Architecture (AMBA) in 1996. AMBA is now in its third generation, with significantly improved speed over the first iteration. IBM developed its own CoreConnect standard for its Power chip architecture.

For chip developers, the nice thing about both bus architectures is that they’re free and well documented. AMBA 3.0 actually includes five different bus interfaces, most notably the Advanced High-performance Bus (AHB), which permits such things as burst transfers and split transactions, and the Advanced eXtensible Interface (AXI), which focuses on addressing and data phases. CoreConnect, meanwhile, includes a processor local bus, an on-chip peripheral bus and a device control register bus.

The advantage—and the disadvantage—of buses is that they’re hard-wired through a crossbar switch. While that guarantees a connection, there are fairly regimented ways of making those connections. For example, you can’t just connect a 32-bit IP core with a 64-bit interface without a converter, and you can’t just match up components with different frequency without using a clock converter.

“Ultimately, a bus performs the same task as a network on chip,” said Mike Dimelow, director of marketing for ARM’s processor division. “Their ways of solving the interconnect issue are different, though. They are both complementary and competitive with each other, but the problem they are trying to solve is the same—connectivity.”

They’re also a way of adding re-usability for IP, which is why Xilinx is now adding support for the AMBA bus architecture in its FPGAs—the last of the major FPGA vendors to support AMBA (both Actel and Altera have supported AMBA for years, while Xilinx backed the IBM CoreConnect approach). One of the attractive things about AMBA is its support for IP-XACT, the IP interoperability standard created by the SPIRIT Consortium (now part of Accellera).

“What this allows us to do is standardize on an interconnect scheme,” said Vin Ratford, senior vice president for worldwide marketing and business development at Xilinx. “FPGAs are a repository for a lot of IP. AMBA is one element for allowing more reusable IP.” (See Figure 1)

Figure 1: AMBA's IP connection (Source: ARM)

Adding flexibility

Building on the need for pre-configured connectivity, networks on chip have taken that approach a couple steps further by decoupling the transaction from the transport, and more recently decoupling the entire physical layer. The approach follows the broader networking world, where information is packetized into discrete bundles rather than maintaining a constant connection the way old telephone lines used to do. (For a look at life before packetization, check out some of old political thrillers where the telephone was kept off the hook one a connection was made to make sure that communication would not be interrupted.)

Decoupling of all those pieces allows a much more flexible design, and both Sonics and Arteris have been pitching the value of different NoC approaches. Sonics joined forces with Synopsys in June to create a pre-configured IP block that includes a memory scheduler and Synopsys’ Designware protocol controller IP. Arteris upped the ante in the NoC world in August, rolling out a peripheral NoC that instantly connects timers, USB, infrared interfaces and audio and touch-screen components.

The advantage of NoCs is a reduction in the number of wires and the flexibility of the design. “What this provides is ultimate flexibility,” said Geert Rosseel, chief technology officer at Arteris. “There is no topology or configuration you have to worry about up front, so in the end this can lead to truly smaller chips with higher frequency. You get big improvements with power, area and performance by using this approach.” (See Figure 2)

Figure 2: The NoC approach. (Source: Arteris)

That’s particularly useful from an architectural level when not all the functions or connectivity that ultimately will be required are known. In some cases, new standards or interfaces are completed before a chip reaches tapeout, and having the flexibility to add onto the design at a later stage is invaluable—particularly when the design will be used for a series of derivative chips.

ARM, meanwhile, is hedging its bets on both the bus and NoC. While it continues to update and support AMBA, its QoS now supports both, according to Dimelow.