Challenges and future directions for disaggregating SoCs.
Projections about the amount of energy required for AI in data centers and other electronic devices are putting a spotlight on more efficient electronics. But making chips and systems more efficient is an enormous challenge. It used to be as simple as turning down the voltage or moving to the next process node, but those approaches are no longer yielding the same kinds of benefits as in the past. Andy Heinig, head of department for efficient electronics at Fraunhofer IIS/EAS, talks the impact of disaggregation and chiplets, where the pitfalls are with partitioning and modeling, and what’s missing out of the design flow today to enable better efficiency.
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