Manufacturing Bits: Dec. 6

Magnet record; IEDM potpourri; 7nm; gate-all-around FETs.


The National High Magnetic Field Laboratory (MagLab) has broken an unofficial record for the world’s most powerful hybrid magnet.

The 33-ton system, called the series connected hybrid (SCH) magnet, has reached its full field strength of 36 tesla. The SCH is more than 40% stronger than the previous world-record hybrid magnet. Tesla, or T, is the measurement of magnetic field strength. A refrigerator magnet has a field of 0.01 T. A typical MRI machine is 1.5 to 3 tesla.

The world-record 36-tesla series connected hybrid before being lowered into its cryostat. (Source: MagLab)

The world-record 36-tesla series connected hybrid before being lowered into its cryostat. (Source: MagLab)

The SCH is not the world’s strongest continuous-field magnet. This record still goes to MagLab’s 45-tesla magnet.

Dozens of measurement techniques can be performed at MagLab’s user facilities. MagLab is funded by the U.S. National Science Foundation (NSF) to develop magnet technologies for the scientific community.

Magnets are used to study materials, chemical compounds and biological processes. These processes are revealed when a specimen is exposed to high magnetic fields. The high fields are created by running electrical current through conductors.

Like the MagLab’s flagship 45-tesla magnet, the SCH combines two types of magnet technologies–superconducting and resistive. Resistive magnets are made of conventional conductors like copper and silver. Superconducting magnets are made of special materials, such as niobium-tin.

The SCH is expected to become the strongest magnet for use in nuclear magnetic resonance (NMR) spectroscopy. For this, scientists use magnets and radio waves to locate a specific element in proteins and other samples. This, in turn, helps them figure out those complex structures.

Current NMR magnets are limited to locating just a handful of elements, notably hydrogen, carbon and nitrogen. The SCH has greater sensitivity, which will enable it to locate zinc, copper, aluminum, nickel and gadolinium. The big breakthrough is oxygen. “There’s going to be a real increase in the reach of NMR into the periodic table,” said Tim Cross, a researcher at MagLab. “So we’re going to be able to look at many more elements than we’ve really been able to in the past. Oxygen is where so much biological chemistry takes place, and until the SCH, we’ve just not been able to look at it.”

7nm race
At this week’s IEEE International Electron Devices Meeting (IEDM) in San Francisco, TSMC as well as the team of GlobalFoundries, IBM and Samsung separately presented papers on 7nm finFET technology.

As expected, TSMC presented a paper on a 7nm finFET platform for mobile applications. The technology provides >3.3X routed gate density and 35% to 40% speed gain or >65% power reduction over the company’s 16nm finFET technology, according to TSMC.

A fully functional 256-Mbit SRAM test-chip with the smallest high density SRAM cell of 0.027um2 is demonstrated down to 0.5V.

Not to be outdone, GlobalFoundries, IBM and Samsung presented a 7nm finFET paper. It makes use of extreme ultraviolet (EUV) lithography. The technology from the companies has a contacted poly pitch (CPP) of 44nm/48nm and a metallization pitch of 36nm.

The process features dual strained channels. This is done on a strain relaxed buffer (SRB) substrate with a super steep retrograde well (SSRW). It also makes use of a tensile-strained NFET and a compressively-strained medium-Ge content PFET, enabling high mobility and the desired drive currents.

The process makes use of a mix-and-match patterning scheme. “For 1D structures like the fin, self-aligned quadruple patterning (SAQP) has been adopted,” according to the paper from the companies. “For quasi-1D structures with more complex layouts but larger pitch, such as the gate, self-aligned double patterning (SADP) is chosen.”

EUV has been used for patterning the middle-of-line (MOL) and lower back-end-of-line (BEOL). EUV has more than 20% improvement in terms of a process window for depth of focus (DOF) at 5% exposure latitude, compared to optical lithography, according to GlobalFoundries, IBM and Samsung.

GAA race
At the 5nm node, there are two main transistor contenders–the finFET and the lateral gate-all-around FET.

In fact, the momentum is building for gate-all-around in the industry. Gate-all-around, sometimes called the lateral nanowire FET, is a finFET on its side with a gate wrapped around it. But there are some major challenges for this technology.

Not long ago, Imec demonstrated gate-all-around FETs, based on vertically-stacked, 8nm diameter silicon wires. These devices were fabricated on bulk silicon substrates for NFETs and PFETs separately.

At IEDM, Imec will describe the integration of both device types–NFETs and PFETs–on the same wafer. The R&D organization will also demonstrate matched threshold voltages for both NFETs and PFETs. This is based on a nanowire-compatible, dual-work-function metal (DWFM) integration scheme.

The technology features matched threshold voltages for N- and P-type devices. “The VT setting is enabled by nanowire-compatible dual-work-function metal integration in a high-k last replacement metal gate process,” according to Imec. “Furthermore, we demonstrate that N- and P-type junction formation can influence nanowire release differently due to both implantation-induced SiGe/Si intermixing and doping effects. These findings underline that junction formation and nanowire release require co-optimization in GAA CMOS technologies.”

Also at IEDM, Leti presented a paper on a gate-all-around technology that also stacks horizontal silicon nanowires. The process makes use of 300mm silicon-on-insulator (SOI) substrates.

Leti has been developing this technology for some time. The R&D organization appears to have addressed one of the major road blocks– parasitic capacitances.

In the process, Leti introduced the integration of inner spacers. This is key in order to reduce gate-source/drain capacitance, according to Leti. “In this work, we introduced, for the first time, inner spacers and SiGe S/D in a RMG stacked wires process. Wider, thinner and stacked wire structures have been proven to be efficient to match or exceed finFETs performance due to higher Weff/footprint ratio,” according to Leti.

In addition, Leti presented a paper on the correlation between endurance, window margin and retention of resistive RAM (ReRAM). ReRAM, a non-volatile random-access memory, is a candidate to replace flash for both standalone storage applications and embedded products. ReRAM enables high density chips with good endurance.

But combining key features, such as sufficient cycling and stable retention at high temperature, is a major challenge for ReRAM. In the lab, Leti identified three correlated parameters that influence performance of ReRAM–the number of cycles that ReRAM can reach; the stability in temperature; and the ratio between the two states of the memory.

By manipulating the material stack, researchers were able to address various non-volatile memory applications, targeting high speed, high endurance or high stability. Leti investigated various classes of ReRAM, such as OxRAM and CBRAM. The project determined the best performance in each category. “In this work, we demonstrated how physics rules memory features and performances,” said Luca Perniola, head of Leti’s memory component lab. “Universal behaviors and tradeoffs are clearly identified, putting boundaries on the best memories tailored for various specific applications.”

Related Stories
What Transistors Will Look Like At 5nm
As finFETs run out of steam after 7nm, what comes next? The debate is just beginning.
Sorting Out Next-Gen Memory
A long list of new memory types is hitting the market, but which ones will be successful isn’t clear yet.
Manufacturing Bits: Nov 29, 2016
Supersonic kinetic spraying; tiny electron gun.


memister says:

At 6% exposure latitude, the EUV and optical process windows are the same.

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