Manufacturing Bits: June 24

A cup of sub-wavelength images
The National Institute of Standards and Technology (NIST) and the University of Michigan have developed a technology that could enable sub-wavelength images at radio frequencies. Researchers used a mere glass cup, and laser light at optical wavelengths, to measure and image RF fields.

In the future, this technology could measure the behavior of metamaterials. It also could lead to new microscopy systems and imaging sensors.

The technology could solve a major problem. Today’s RF imaging requires dipoles, probes and reference antennas, but there are limitations in terms of imaging and overall resolution.

The new technique from NIST and the University of Michigan makes use of lasers and rubidium atoms as tunable resonators. In the experiment, the rubidium atoms are placed in a hollow glass cylinder. A red laser excites the atoms. This, in turn, causes light to be absorbed.

Laboratory apparatus for mapping and imaging of radio frequency (RF) electric fields at resolutions below the usual RF wavelength limit. Rubidium atoms are placed in the glass cylinder (on the right), which is illuminated at opposite ends by red and blue laser beams. (Source: NIST)

Then, a tunable blue laser excites the atoms to one of many possible higher energy states. “Next an RF field—at the frequency to be mapped or imaged—is applied,” according to NIST. “This field alters the frequency at which the atoms vibrate, or resonate, altering the frequencies at which the atoms absorb the red light. This change in the absorption is easily measured and is directly related to the electric field strength at that part of the cylinder. By moving the cylinder sideways on a track across the narrow laser beams, researchers can map the changing field strength across its diameter. The blue laser can be tuned to excite the atoms to different states to measure the strength of different RF frequencies.”

In current systems, RF field measurements are averaged over antenna dimensions of tens of millimeters or more. NIST’s prototype technique has resolution in the range of 50 to 100 micrometers. In fact, the technology was used to map RF fields with much longer wavelengths of 2,863 and 17,605 micrometers, or frequencies of 104.77- and 17.04-GHz, respectively, according to NIST.

Making better TSVs for 3D ICs
The development of advanced 2.5D/3D chips using through-silicon vias (TSVs) remains a challenge.

There are several issues with advanced stacked die. Thermal issues, test challenges, stress and costs are problematic. To decrease the stress levels, TSVs with aspects ratios greater than 10:1 are required. But for enabling a continuous copper seed layer for high-aspect ratio TSVs, physical vapor deposition (PVD) tools are approaching the limits, according to some experts.

On the other hand, Applied Materials recently introduced the Endura Ventura PVD system that helps chipmakers reduce the cost of 3D chips. The system incorporates Applied’s latest PVD technology that enables the deposition of thin, continuous barrier and seed layers in TSVs.

In a separate effort, Imec and Tohoku University have demonstrated the feasibility of a copper electroless deposition (ELD) technology for a TSV metallization process. More specifically, researchers investigated the application of a glyoxylic acid based ELD-copper process on CVD-ruthenium (Ru) and CVD-cobalt (Co) nucleation layers for TSV metallization

The copper electroless plating bath uses glyoxylic acid as a reducing agent, according to researchers. Patterned structures used in the experiments consisted of TSVs with a 3um diameter and 50um diameter with an aspect ratio of 16.7. The nucleation or pre-seed layers were CVD-Ru or CVD-Co, which had thicknesses of 10nm and 30nm, respectively.

When using PVD-copper as a seeding layer for the copper plating process, the minimum in-field thickness needs to be 1500nm to guarantee step coverage at the bottom of the TSV, according to researchers. But according to researchers, the overburden after electrochemical fill with copper on the ELD-copper seed was 50% lower than traditional PVD.

“(A) much thinner and continuous Cu seeding is obtained using the ELD-Cu seed approach. The thickness of the ELD-Cu film is about 110nm at the top and 50nm at the bottom of the TSV,” according to the research paper. “Moreover, the ELD-Cu appears to be continuous even though the initial Ru was thin and couldn’t be detected by TEM. As the Ru serves as (a) catalyst for the ELD-Cu deposition reaction, the layer thickness can be thin (sub-2nm), as long as it is metallic and continuous throughout the structure.”

CVD-Co has also attracted interest as an alternative material for seeding, but the combination of ELD-Cu on CVD-Co has not been investigated extensively. “Co is not compatible with acidic, and it has more negative redox potential than Cu. For these reasons, the ELD-Cu process also needs to be optimized in order to enable deposition on Co,” according to the research paper.

Researchers looked at the cross-sectional TEM images of a TSV before and after ELD-copper on the cobalt. “The Cu overburden in the field needed to complete the filling was about 600nm. Compared to using PVD-Cu seeding layer with in-field thickness up to 1500nm, the total Cu stack is much lower and this will reduce the CMP process time,” according to the paper.

Meanwhile, Sematech and Atotech presented slightly different results. In a separate paper from the two entities, a study of electroplating high aspect ratio TSVs with a Ru seed layer on 300mm wafers was presented. PVD of about 100nm copper in the field was shown to improve plating non-uniformity across the structured wafer. TSV plating using Atotech’s TSV III chemistry resulted in bottom-up growth with good TSV sidewall suppression and void free TSV fill.

Copper plating was performed using a 300mm tool. The plating bath was built using Atotech’s TSV III chemistry comprising of Cuprabase60P base electrolyte, and three component organic additive suite: Leveller 10, Carrier 11 and Accelerator 10, according to Sematech and Atotech.

In this study, wafers with 5 × 50μm TSVs with a TEOS dielectric liner and a TaN/Ta/Ru barrier-seed film stack were used. “As a last pre-plate metallization step and to mitigate terminal effect, 60-100nm PVD Cu was deposited in the field under very low bias voltage. Since PVD processes are highly directional, most of Cu deposits will occur on the planar surface under this condition,” according to the paper.

“Cu plating was done using Atotech’s TSV III chemistry and the terminal effect phenomena was studied based on overburden (OB) thickness measurements for TSV cross-sections from three locations on the wafer,” according to the paper. “Direct Cu plating on 3nm Ru (without field Cu) resulted in a significant plating non-uniformity across the wafer due to the high resistivity of the Ru seed. The measured drop in OB from edge-to-center locations is ~32 %. TSV bottom void and pinch off were observed at center and edge locations respectively. However, with 60 and 100nm Cu in the field, plating uniformity across the wafer greatly improves.”