Manufacturing Bits: Oct. 21

Peanut butter and chocolate TEMs
Lawrence Livermore National Laboratory, Johns Hopkins University and the National Institute of Standards and Technology (NIST) have developed a new microscopy technology that combines two types of key measurements.

The technology, dubbed the dynamic transmission electron microscope (DTEM), captures information about both temperature and the crystal structure during a reaction in thin-film materials. The DTEM could be used in semiconductor and flat-panel display applications.

Graph shows heat absorbed by a thin film of aluminum as its temperature increased. Inset boxes show electron diffraction patterns captured by DTEM as temperature changes. The patterns reveal the crystal structure and orientation of the aluminum. (Source: NIST)

The DTEM combines a TEM and nanocalorimetry technology. In a traditional TEM, diffraction and transmission patterns are made by electrons passing through a sample. But TEMs require that the sample maintain one crystal structure for an extended period, according to NIST.

In a thin film, nanocalorimetry can track large temperature changes at rates up to 1000 degrees Celsius per millisecond. This, in run, can track a material’s phase transitions. But nanocalorimetry tells researchers little about the actual chemical processes, according to NIST.

To enable the DTEM, researchers shrunk the separate circuitry for the nanocalorimeter to a tenth of its original size. This is so it could fit inside the TEM-based microscope. All told, the combined TEM/nanocalorimetry technology captures phase transitions and structural changes at a fast rate. It relies on a pulsed laser to send short, bright blasts of electrons through a sample.

“It’s like peanut butter and chocolate,” said David LaVan, a NIST materials scientist, on the agency’s Web site. “If we can somehow get these two instruments working simultaneously, we’ll have the whole story.”

In one of the first experiments, the DTEM ran tests on aluminum. The measurements were consistent with the materials’ known properties. Recently, scientists have used the DTEM to measure the combination of aluminum and nickel in thin-film alloys.

Tornado chips
The University of Sheffield has demonstrated magnetic logic gates. In the technology, magnetism becomes “swirling tornadoes” of magnetization known as magnetic vortex domain walls, according to researchers.

Magnetic logic gates process binary data. This data is encoded within the internal magnetization structure of domain walls in ferromagnetic nanowires, according to researchers. In the nanowires, domain walls form magnetic vortices. More specifically, the magnetization circulates either clockwise or counterclockwise.

By exploiting differences in how these two domain-wall structures react, researchers can design nanowire segments that act as NOT, FAN-OUT, NAND, and, or, and NOR logic gates.

The gates could be cascaded to perform any desired logic operation. Researchers now plan to build experimental prototypes of the logic gates. They will investigate whether they can be made smaller and operate faster. “While this technology is at a very early stage, and a huge amount of work is still to be done, we have demonstrated an entirely new way of both storing and processing information. We’re now looking forward to moving towards experimental prototypes, and exploring whether we can make real devices that are much more power efficient than those in current computers,” said Tom Hayward from the University of Sheffield, on its Web site.

3D gate-all-around
Gate-all-around FET is a promising transistor candidate for the 7nm node and beyond. But at present, the problem is that the drive current of each gate-all-around device is limited by a reduced channel area, according to National Cheng Kung University in Taiwan.

To get around the problem, National Cheng Kung University has developed a stacked silicon nanowire MOSFET. The MOSFET, which can be classified as a gate-all-around FET, also makes use of a silicon-on-insulator (SOI) substrate. A flexible doping scheme has also been devised to enable high-performance and low-operating power designs with the technology.

Using silicon/silicon-germanium superlattice epitaxy and an in-situ doping process for stacked wires, researchers have developed a stacked, four-wire gate-all-around FET. The gate-length for the device is 10nm. Both the channel width and the height are 10nm, based on an electrostatic scale length of 3.3nm. The device has an off-state current (Ioff) ≤100 nA/μm at VDD=0.68 V.

“Threshold voltage doping (schemes) for stacked wires is far different than for conventional approach, especially when multiple layers of transistors are integrated on the same substrate,” according to a paper from the university. “Leaving the channel undoped has an advantage in mobility and is expected to relieve the issue of random dopant fluctuation, but it does not meet the need for multi-Vt design being commonly used in SoC applications. Instead, different gate work functions (or gate materials) will be needed for different Vt’s, and hence, such undoped approach would be even more complicated.”

Researchers have implemented a different approach. “During epitaxy process, the in-situ doped channel is implemented for each of the stacked wires,” according to researchers. “Doped stacked-GAA MOSFETs provide flexible options for Vt adjustment.”