Material And Process Challenges In A Changing Memory Landscape

Moore’s Law has fueled the semiconductor industry’s growth for decades. But as the complexity of scaling increases, extending the economics of Moore’s Law is becoming a challenge.

One example illustrating the challenges of maintaining the economic benefits of Moore’s Law is the difficulty of IC chip patterning. Today, this requires an expensive litho scanner, a complicated spacer and hard mask stack film using CVD/ALD deposition, precision etching, and chemical cleaning in the gas phase from traditional litho scanner, etching and chemical cleaning in the wet phase. These process changes increase overall chip manufacturing cost dramatically to maintain small features with high integrity.

On the other hand, demand for IC chips with more efficient computing and high functionality remain unchanged. This creates opportunities for additional vectors other than traditional ones for the semiconductor industry to follow. Examples include novel packaging schemes in which IC functions, such as high bandwidth and power consumption reduction, are enhanced by RC bottle-neck and increasing accessibility between different functional chips such as fast logic core and high-density memory banks, and which can be done at a lower cost with interposer and through silicon via (TSV).

Additionally, changes in system and design are being made to maximize the functions of IC chips to meet the increasing computing demand for faster connection to large amounts of data with very low power consumption. Changes include increasing the number of cores to provide computing power to support complicated simultaneous computing, and adding specifically functional chips — graphics and communication processors into the main IC chip, providing combined capabilities that improve the overall performance of each individual chip.

Nevertheless, these changes still fundamentally use the same device (CMOS and memory) and architecture (data access through memory and computing through digital logic) that rely on geometric scaling to reduce cost or increase function. The logical question for the industry to answer is if there are additional opportunities other than the above to help continue Moore’s Law.

Recent progressions made in CMOS technology point to several inflections. Key among these is more and more new materials such as strain silicon, high-k gate dielectric and metal gate, Co metal interconnect, AlN etch stop and Cu barrier dielectric are being used to create robust basic chip components. These material additions are now necessary to maintain Moore’s Law in order to meet market demand for more functions.

So, is there more room on the die to facilitate the greater functions derived from the new materials? And if so, what and how? One option would be an advanced CPU chip in which high-density SRAM is integrated for more computing function at high speed. SRAM is a volatile memory technology that is comprised of 6-8 transistors. The area of silicon used to make them is correspondingly large at 0.05um² for 14nm technology compared to a 20nm technology DRAM that uses one transistor silicon area at 0.0036um². This provides a tenfold savings of silicon area if the integration of one transistor memory can meet function and cost requirements. However, making DRAM for a case such as this has been shown to be quite expensive, and DRAM refresh requirements further impact the overall chip functionality.

Additionally, there is high interest in integrating a Spin-Torque-Transfer-Magnetic RAM (STT-MRAM) as another possibility of using one or two transistor silicon area to allow a high-density memory to enhance the functionality of the chip while saving the silicon area at a small added cost to integrate. Due to the change of the memory operation mechanism that uses magnetization in STT-MRAM, non-volatility can be used to enhance overall computing. However, this comes with the requirement of applying new magnetic materials for both deposition and etching, which is a challenge for high-volume manufacturing.

Low cost has been a driving force for DRAM and flash for a long time, while the functions of these devices have remained similar. The pace of DRAM cost reduction has deviated from Moore’s Law for some time as the manufacturing cost has dramatically increased due to primarily litho-driven miniaturization. Moreover, this pace is expected to slow down further in the coming year and could potentially stall.

Flash, mainly with NAND devices, has managed a fast pace at doubling the density every 18 months for 2D NAND before 2010, and has recently resumed the traditional pace with the adoption of 3D NAND. Although there are no significant material changes in the 3D NAND process, the degree of difficulty of using the same material has escalated. As the vertical dimension is used for scaling, the structural requirements pose significant challenges for processes such as deposition and high aspect ratio etching. A 1:1 aspect ratio means the vertical dimension is the same as the lateral dimension. For 3D NAND, this ratio is moving to 50:1 and 100:1 as vertical scaling continues. For a high aspect ratio structure, the process reactant typical in CVD/ALD deposition and the reactive ion etching processes need to travel very long distances in small spaces to yield reaction. This makes it more difficult for the processes that need plasma to activate the reaction.

Finally, as computing advances to a more power efficient era, one of the other long-standing inefficiencies between processor and memory needs to be addressed. This provides the opportunity for a new device to emerge. A device called storage class memory, which is characterized with a combination of DRAM for fast data access and NAND for data retention, has recently received a lot of attention for future computing. Although the integration of DRAM and NAND at the system level can fill in the gap to a certain extent, it is fundamentally not efficient for cost as this uses two memories instead of one and an additional controller. To control cost, some of the fast non-volatile memories such as PCRAM and ReRAM are being considered for integration in 3D structures with CMOS circuity to offer lower cost and higher performance than the combination of DRAM and NAND. As the operation mechanisms are significantly different, new materials, such as chalcogenide phase change materials, noble metals iridium, platinum and silver, sub-stoichiometric transition metal oxide, are commonly used to yield more power efficient operation of the memories. Precision control of material is therefore needed for manufacturing, such as alloy composition control for phase change memory, local oxygen vacancy control for OxRAM, and metal ion drift control for CBRAM. These controls are further needed in various 3D structures among which extremely high aspect ratios require a novel etching solution to enable the device integration.