Meeting The Challenge Of Verification In Low-Power Designs

Lack of standard unified flow for low-power design and methodology creates challenges; some progress is being made.

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By Cheryl Ajluni
Over the years, new techniques, technologies and design tools have been brought to market with the explicit intent of simplifying design verification. Despite these efforts verification still manages to consume a huge chunk of the time spent during design. By some accounts that number tops 70%.

The problem is that verification is hard, and it certainly doesn’t get an easier when we move into the low-power design realm. Low-power design techniques have become increasingly complex and, in the process, have led to an explosion in verification complexity. As a result, low-power verification is now the key challenge in low-power design. As Ying-Chih Yang, technical director of Home Entertainment Products at Sunplus Technology points out, “Because power consumption is one of the most critical factors of today’s SoCs for mobile applications, the ability to accurately verify low-power functionality is essential to achieving first-pass silicon success.”

The low-power design challenge is complicated by the fact that there are many problem areas that need to be addressed. Consider the use of Intellectual Property (IP), for example. In the past, designers could throw IP together and be comfortably assured that things would work okay. Now, because of the heavy concentration on low power, if a design with IP is not properly verified, the designer runs the risk of throwing off their power budget or worse yet, ending up with non-functional silicon. The key here is proper verification. But with no well-defined or widely accepted low-power design and verification flow, it’s hard to agree on exactly what issues that verification flow needs to address.

Ashwin Matta, director of IP Verification at Denali Software, says one of the challenges associated with the verification of IP in low-power designs is that it “needs to support special features for power optimization. Addressing this problem requires an investment in a state-of-the-art verification methodology and tools that verify the correctness of low-power IP behavior.” To prove this statement, he points to the example of a memory subsystem, which is a major source of power consumed on a low-power chip. The subsystem consists of a memory controller talking to external low-power DRAM memory that supports a variety of low-power modes (e.g., power down and self-refresh). A combination of hardware and software interfaces is used to exercise these low-power modes.

“Software control of low power requires that the driver software detect the need to save power, possibly due to low density of memory traffic, and then program the controller to enter the appropriate power-saving mode,” says Matta. “Software can exercise fine-grained control of power entry and exit, providing considerable power savings without an appreciable loss of performance associated with exiting a low-power mode. Hardware interfaces are necessary for more catastrophic events such as a sudden loss of power to the chip. Under such conditions, software control isn’t possible and the controller is required to put the memory into self-refresh mode to prevent data loss or memory corruption.”

From a verification perspective, being able to test the controller for function and performance under all possible conditions of hardware- and software-controlled low-power operation is absolutely vital. Adds Yervant Zorian, Virage Logic’s chief scientist: “Because today’s SoCs include an ever-increasing amount of embedded memories, the need for an integrated embedded memory test and repair solution that can identify and repair faults is critical as companies seek to ramp to volume at the advanced process nodes.”

But this is not the only verification concern when it comes to IP. Ensuring IP functions according to a design’s power intent, for example, requires that it be verified throughout the design implementation flow using the same constraints format. A heterogeneous tool environment and flow is also required (See figure 1). As Kiran Vittal, director of product marketing for low power & test products at Atrenta explains, “Here power intent can be captured in standard formats like CPF or UPF for implementation and verified at RTL, gates or post layout with structural verification or simulation tools.”

Figure 1. SpyGlass-Power is a structural verification solution that supports power intent constraints through SGDC format (SpyGlass Design Constraints, in use since 2004), CPF and UPF. For effective verification in low-power designs, IP needs to be verified in heterogeneous tool environments and power intent formats as shown here.

Figure 1. SpyGlass-Power is a structural verification solution that supports power intent constraints through SGDC format (SpyGlass Design Constraints, in use since 2004), CPF and UPF. For effective verification in low-power designs, IP needs to be verified in heterogeneous tool environments and power intent formats as shown here.

Another area of concern is interface IP like PCIe and USB 3.0, which include power management features and low-power states that must be verified like any other protocol feature. Or so says Neill Mullinger, group marketing manager at Synopsys, whose responsibility includes verification IP and methodology support. “This requires additions to the testbench to verify the correct transitions through the low-power states,” says Mullinger. “Verification IP must support the low-power features needed to test the interface IP’s low-power capabilities and verify the design is transitioning to low power as documented in the protocol specifications.”

Of course, ensuring all of these concerns are adequately addressed would be a lot easier if the industry agreed on a low-power design and verification methodology and flow. As Erich Marschner, manager of low-power and static/formal verification solutions at Mentor Graphics explains, “Today, most design teams define their own ad hoc flows that incorporate legacy methods, depend on proprietary languages and tool features, and often result in incomplete verification of the low power aspects of the design. They continue to look for new verification methods to address holes in their flow, but incremental patches are not going to be sufficient in the long run.”

One possible answer to this dilemma lies with the IEEE 1801-2009 (UPF 2.0) standard for design and verification of low-power ICs. According to Gary Delp, chair of the IEEE P1801 standard, “UPF provides conservative simulation semantics. So, when the UPF is written to describe a design, the simulator makes sure that sources of potential corruption, structural errors or inconsistencies are pointed out. When the same description (along with the rest of the design) is used to implement the design, the implementation requirements are also conservative. Thus, the simulation semantics provide a bounding box for the implementation whereby it must safely operate under all of the specified conditions, and provide logical accuracy whenever the simulation does.”

Such a low-power design and verification methodology and flow is crucial to enabling low-power verification tasks to be accomplished much more easily and effectively, but even without it low-power verification tasks are getting done. One such task is voltage-aware simulation. According to Krishna Balachandran, director of low power verification marketing at Synopsys, “Non-low-power designs are verified for functionality without any regard to operating voltages. Low-power design techniques, on the other hand, use voltage to control power and as a result verification done without considering voltages can’t find the low-power bugs that may be lurking in a design.” Voltage-aware simulation plays a key role in allowing engineers to consider voltages during verification.

Some of the other verification tasks being addressed include:

Modeling different use modes (e.g., the MP3 or active call mode in a cell phone) to meet a specific power budget. In addition to their modes of operation, low-power designs have many power modes. These modes can affect the circuit’s function and must be properly verified, but doing so implies that all intended combinations of power and operating modes must be verified, If not, various problems can arise (e.g., data loss, dead lock conditions or unpredictable behavior).

An early power analysis of an application’s different use modes during architecture planning and chip assembly is one way to attack this problem Another way, according to Neil Hand, director of low power solutions marketing at Cadence, is through power-aware metrics-driven verification. With this approach, “the power intent of the design is captured, usually in a format such as CPF. This power intent is then used during verification to ensure that the design behaves as it would with all of the power-control logic in the RTL. It is also used to infer all of the power modes that need to be covered in the design, creating the appropriate coverage metrics and assertions automatically. Verification then continues as normal, only now it is fully power-aware.”

Verifying power-management elements. Low-power designs often introduce power-management elements that are not part of the original design specification. Verifying the functionality of these elements, along with their correct insertion and connection, can be quite challenging. Here, static low-power verification tools can be used to check and report errors in the implementation of the elements in comparison to the design’s power intent throughout the design flow. Static equivalence checkers can also prove useful—ensuring that following insertion and connection of any elements, the design is functionally equivalent and performs the power-management function as specified.

Even if the industry can get closer to a low-power design and verification flow, it doesn’t address the problem of education. After all, one of the reasons that verifying low-power designs is such a difficult task for today’s verification engineers is that most are not yet well trained on low-power concepts. There may be some truth to this, but a range of tools are now available that can help guide the engineer through the steps necessary to address many of the challenges in low-power verification. Some of the vendors currently offering solutions include:

➢ Atrenta: ITeam Genesis and Spyglass platforms for power analysis, optimization and verification.
➢ Cadence Design Systems: Incisive Enterprise Verification, Conformal Low Power, Palladium PDA, and Encounter Power System.
➢ Denali Software: Configurable and fully verified low-power memory controller IP.
➢ Mentor Graphics: Questa verification platform.
➢ Synopsys: MVCIM with VCS, MVRC and Formality.
➢ Virage Logic: STAR Memory System, advanced semiconductor IP solutions.

There is little doubt that low-power designs have had a profound impact on verification. Addressing the challenges this creates is no easy task, but creation of a low-power design and verification methodology that the industry can rally behind and that tool vendors can support is a good starting place. It will be crucial to dealing with verification of IP, among other tasks, during low-power design.