Meeting The Demands Of PAM4 Systems At 56Gbps And Beyond

According to an IDC white paper sponsored by Seagate the global datasphere will grow from 33 zettabytes (one zettabye = one trillion gigabytes) in 2018 to 175 zettabytes by 2025. This white paper also reports that today, more than 5 billion consumers interact with data every day. By 2025, that number will be 6 billion, or 75 percent of the world’s population. Figure 1 depicts this exponential growth. In 2025, each connected person will have at least one data interaction every 18 seconds. One last fact from this white paper: If you could download the entire 2025 global datasphere at an average of 25Mb/s, today’s average connection speed across the United States, it would take one person 1.8 billion years to do it.

Clearly, there is a data explosion occurring with an ever-increasing requirement for dramatic bandwidth improvement to keep up. In this white paper, we’ll explore some of the requirements to implement dramatic bandwidth improvements, Technology, methodology and strong collaboration all play a part.

Our discussion will focus on PAM4 (pulse amplitude modulation) systems operating at 56 Gigabits per second and beyond. PAM4 is a modulation technique whereby four distinct pulse amplitudes are used to convey the information. PAM4 enables twice the transmission capacity when compared to binary modulation. Because the additional voltage levels in PAM4 reduce the level spacing by a factor of three, PAM4 is more susceptible to noise than a binary digital signal, thus requiring a higher signal-to-noise (SNR) ratio. Consequently, PAM4 is normally used for short-reach applications where a higher SNR can be obtained.

We will explore how this shortcoming can be overcome, resulting in very long-reach signaling with PAM4 encoding over a copper cable to enable next-generation 25.6 and 51.2Tb/s switches, routers and 800G systems. Delivering this capability has two challenges — working silicon that can deliver the required performance and a SerDes test fixture that allows system designers to verify performance in their target application. We will discuss both challenges.

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