Mentor TLC NAND Softmodel Soft-Bit Error Injection

How to simplify the design and verification of SSD controllers.

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Designing SSD controllers targeting NAND flash as the storage media requires some heavy lifting when it comes to dealing with the soft-errors that the flash will eventually produce. This paper will look at a method to simplify the design and verification required. We model these soft-bit behaviors with the Veloce emulator in a virtual setup, which reduces the time to market for an SSD.

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