How to simplify the design and verification of SSD controllers.
Designing SSD controllers targeting NAND flash as the storage media requires some heavy lifting when it comes to dealing with the soft-errors that the flash will eventually produce. This paper will look at a method to simplify the design and verification required. We model these soft-bit behaviors with the Veloce emulator in a virtual setup, which reduces the time to market for an SSD.
To read more, click here.
 |
 |
 |
 |
 |
 |
 |
 |
 |
Leave a Reply