Mix-And-Match Power Options

By Ann Steffora Mutschler
Choices abound today when it comes to considering a node shrink. Fully depleted silicon on insulator (FD-SOI) and finFET technologies along with other advanced transistor options are being evaluated, both together and independently of the other. It is possible to implement finFET on bulk 28nm CMOS or finFET on an FD-SOI process, for example. It is also possible to implement 20nm planar CMOS with or without finFET and with or without FD-SOI.

“From a high-level perspective, the FD-SOI has to do with how the substrate and the wells are all manufactured, but that’s below where the finFET is on the gate drain side and they are independent of each other. One looks at how the gates are manufactured, and the other is what sits on top,” explained Andy Inness, place and route product specialist at Mentor Graphics. “The FD-SOI is proving to be helping even more than finFET, and especially since they can go together, we are getting to these small gate finFETs, and the isolation from the FD-SOI is helping bring down variability and also improving performance because it gives more predictability to how the wells are going to operate. It’s more isolated and therefore more predictable and less transient current, less leakage current—you get some better performance and more predictability even if it costs you a little bit in manufacturing.”

From the foundry perspective, Subi Kengeri, vice president of advanced technology architecture in the office of the CTO at GlobalFoundries, believes the power benefits of the combination of finFET and FD-SOI is impressive. “For the first time in the history of technology scaling we are actually able to reduce the operating voltage to a comfortable level. We were simply not able to reduce the voltage because of the technology issues. SRAMs would have failed previously. But now, because of the fully depleted device and the finFETs for your low voltage scaling, for example, we dropped the operating voltage 100mV from 20nm planar to finFET. That 100mW makes a big difference to our customers and applications because it has a V squared effect in terms of reducing power. You drop the operating voltage by 100mV—let’s say from 0.9 to 0.8—that’s about a 20% power reduction right there.”

Further, the finFET transistor allows the device to operate at a wide range because it is a fully deplete device and has a lower Vt compared to planar CMOS, as well as smaller random dopant fluctuations that allow for tighter variability control, he said.

With these choices, how do design teams decide what to adopt and when?

“We’ve seen a couple of customers where FD-SOI seems to be the one that they’re gravitating towards first because, from an EDA perspective, from a place and route perspective, it’s almost transparent,” said Inness. “You can almost just map the GDS and just plug in different library cells that are the same footprint, and same everything, but still gain the performance and/or the power benefits from it. You can go from 28 bulk to 28 FD-SOI on the same design and it’s nearly just a direct map. There is minor cleanup, but from a big picture there’s very little difference.”

What this will require from the tools is the understanding that certain cells cannot be placed directly next to certain other cells, depending on the internal cell design, Inness said. “All of the implementation tools need to recognize this, this pairing of cells and how they can be placed against each other. And whether it is double patterning or finFET— both of these are just rules that have to do with how close certain cells can be to what other specific types of cells. Beyond that there isn’t a lot from the implementation side that we really need to comprehend on that transistor side. There’s double patterning, but that’s more on the routing and not specific to finFET and FD-SOI.”

For designers, most of this will be handled by the tools, he said. “From a user perspective there are probably not a lot of updates, but there is a tremendous amount of R&D on how to handle these complex interrelationships. But that’s all under-the-hood stuff that the EDA companies need to worry about. There’s still a fair amount of technology needed to make it transparent to the user.”

However, to say that finFET won’t impact verification really depends how closely you are looking, said Cary Chin, director of marketing for low-power solutions at Synopsys. “Clearly, finFETs are a fundamental change in the way that we’re building transistors. We’re moving from relatively planar technologies to 3D technologies. At a very low level, when you’re looking at tools for building transistor models or for verifying technologies and things like that, there are very significant changes. For the last year or so we’ve been hearing announcements from all of the major foundries in the world and everyone’s moving to this technology. That’s because it has huge promise, especially in the area of low power. That was one of the driving forces for moving to finFETs.”

One of the big challenges is to make new technology as consistent with existing design flows as possible.

“We would like not to have to change the implementation flows too much in order to be able to scale things directly and move designs quickly,” Chin said. “At the low level things are changing a lot so all of the tools having to do with transistor level modeling, library characterization, RC extraction—all of those things that have more to do with the physical side. Even the mask generation and optimization tools on the physical side are changing a lot. If we really wanted to optimize our existing design flows for this technology we could probably milk more out of it, but that would be at the expense of some of the implementation and verification flows. Right now that’s something that we want to do. It makes more sense to build as much of a layer as we can over the technology so we continue to cruise.”

If the industry is successful at building this layer on top of the technology then the SOC or the chip designer will be relatively isolated. “But what’s going to happen is the fundamental transistor technology will be relatively insulated from but all of the design parameters that go along with building more and more effective low-power kinds of designs and are going to become more important,” Chin said. He noted that over the next few years more design time will be spent looking at low-power designs versus high-performance tradeoffs. This comes right back around to finFETs that promise better performance at the same power or lower power—performance can be traded for power.

Essentially, he believes we’re in pretty good shape for finFETs. “There’s a lot of work that’s already been done making the higher-level design – the traditional chip design process –relatively transparent, which is great. Because we’re going to have these technologies available to us in the next five years, it’s going to enable us to do a high-level rework of the tools and continue to push on the idea of integrated power optimization into the flow.”