Two machine learning modeling applications that enhance the accuracy of timing delay and routing congestion estimation for FPGAs.
The FPGA physical design flow offers a compelling opportunity for Machine Learning for CAD (MLCAD) for the following reasons:
• An ML solution can be applied wholesale to a device family.
• There is a vast data farm that can be harvested from device models and design data from broad applications.
• There is a single streamlined design flow that an be instrumented, annotated, and queried at all stages.
In this white paper, two ML modeling applications are provided to enhance the accuracy of timing delay and routing congestion estimation in the Vivado® ML edition. Accurate delay estimation is pertinent for timing closure because the global/detail placer, physical synthesis in placement, and the global router use it to estimate net criticalities. The ML-based delay estimator improves the accuracy from 65.5% to about 98%. The Vivado Design Suite placement flow relies on a routing congestion estimator to identify and alleviate routing congestion hotspots during placement so that the design is easier to route downstream. The ML-based congestion estimator in the Vivado ML edition demonstrates similarly significant accuracy gains over the traditional approaches, and results in marked routing run-time reductions on a broad suite of designs from various device families.
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