Mobile Memory Madness

By Mark LaPedus
The insatiable thirst for more bandwidth in smartphones, tablets and other devices has prompted an industry standards body to revamp its mobile memory interface roadmap.

As part of the changes, the Joint Electron Devices Engineering Council (JEDEC) has scaled back the initial version of Wide I/O technology and pushed out the introduction date of a true 3D stacked architecture until 2015.

In the previous roadmap, mobile DRAMs were supposed to follow a simple progression from the conventional LPDDR2 to the LPDDR3 interface standards. Then, in 2013, the mobile industry was originally supposed to make a giant leap to Wide I/O, a 3D technology using through-silicon vias (TSVs).

Now, in JEDEC’s new roadmap, the industry will extend LPDDR3 with a new DRAM interface standard called LPDDR3E. After LPDDR3E, the industry will follow two simultaneous paths with a pair of new standards: LPDDR4 and Wide I/O-2. Devices built around 2D-based LPDDR4 and 3D-enabled Wide I/O-2 are due out in 2015. The first Wide I/O standard is still on JEDEC’s roadmap, but the devices are expected to be limited and mere point products.

The changes in the roadmap reflect the need to address the current and future bandwidth bottleneck issues in mobile devices. It also confirms the industry is still struggling to develop stacked 3D chips due to cost and technical issues. “It will take more time to sort out (3D issues like Wide I/O) than what people originally thought,” said Pat Moran, memory program manager at Qualcomm, at a recent JEDEC event.

The resistivity problems in planar devices have fueled the development of stacked 3D chips, whether those TSVs run through a die or a separate interposer die in so-called 2.5D chips. In either case, stacking is a viable way to circumvent the resistance-capacitance (RC) problems. But advanced chip stacking has a multitude of challenges and is still a few years away from mass production.

The industry is making progress in terms of reducing the manufacturing costs, and the technical hurdles, for 3D chips, said Niranjan Kumar, product marketing manager for TSV programs at Applied Materials. But when the 3D chips actually hit the market, there is still a perception that the cost of devices will be prohibitively expensive, Kumar said.

A brief history of Wide I/O
Not long ago, the big memory houses mainly focused on selling commodity DRAMs for PCs and servers. But for some time, DRAM makers have been engulfed in a prolonged downturn amid a slump for PCs. And the rapid rise of smartphones and tablets has prompted memory makers to put more emphasis on mobile DRAMs, which are specialty DRAMs with low power features.

In a sign of the growing importance of these parts, mobile DRAM represented 26% of all DRAM sales in the second quarter of 2012, compared to 19% in the like period a year ago, and 11% two years ago, according to IHS iSuppli. Average DRAM content in smartphones will expand to 666 megabytes (MB) this year, up from 453MB in 2011 and 202MB in 2010, according to the firm.

“As smartphones become more sophisticated, memory usage in the devices continues to rise, not only to satisfy user wants and needs, but also to accommodate demands made by ever-more powerful processors and increasingly refined LCD screens,” said Clifford Leimbach, an analyst at IHS iSuppli.

To keep up with the bandwidth requirements in portable systems, OEMs have migrated from mobile DRAMs based on the LPDDR1 interface standard to LPDDR2 technology. LPDDR1 has a data rate of 1.6-GB/s, while LPDDR2 runs at 4.3-GB/s.

In 2008, there were fears that LPDDR2 would run out of steam. So, at the time, the industry pushed a 3D architecture called Wide I/O. Wide I/O was a 4-channel scheme with a data rate of 17.2 GB/s. In the original roadmap, the goal was to stack the devices using TSVs.

Then, in 2010, the mobile market turned upside down, when a new class of smartphones and tablets emerged. Suddenly, Wide I/O, which was originally targeted for high-end smartphones, could only address limited mobile applications. “Wide I/O wasn’t going to cover the entire mobile space,” Moran said.

What’s next?
As a result, the industry saw an urgent need to fill a gap between LPDDR2 and Wide I/O. Starting in 2010, JEDEC and its members began to work on 2D-based LPDDR3, an extension of LPDDR2 that operates at speeds up to 12.8-GB/s in a dual channel mode.

Today, Hynix, Micron and Samsung are sampling their respective LPDDR3 mobile DRAMs. Instead of LPDDR3, some OEMs are opting for a low-power version of a desktop DRAM, dubbed DDR3L. OEMs are expected to migrate towards both technologies in 2013.

Needless to say, the industry must go beyond LPDDR3. The explosion of video, games and other technology in the mobile environment is driving the need for 4G LTE networks. “The bandwidth requirements are steep,” said Jung-Yong Choi, senior product planning manager at Samsung. “We need to react quickly.”

In response, JEDEC has unveiled a new, three-step plan. In the first step, the industry has devised LPDDR3E, an extension to LPDDR3 that has a data rate of 17-GB/s in a dual-channel mode at 1.2 volts.

Following LPDDR3E, the industry will follow two simultaneous avenues. It will take another evolutionary and safe path with 2D-based LPDDR4. It also will pursue the more revolutionary path with 3D-based Wide I/O-2. “Both candidates will have their own positions in the mobile industry,” Choi said.

LPDDR4-based mobile DRAMs, which require more space, are aimed at tablets. LPDDR4 will have 25.6-GB/s data rates and operate at 1.1 Volts. LPDDR4 will have 2-channels per die and 8-banks per channel. The LPDDR4 specification is due out by December of 2013. LPDDR4-based mobile DRAMs are expected in the first half of 2015.

Wide I/O-2 has the same specification and product roll out target dates as LPDDR4. Aimed for smartphones, Wide I/O-2 will launch in two phases. The first devices will have a 25.6-GB/s data rate, followed by parts at 51.2-GB/s.

Wide I/O-2 resembles the same architecture as the original Wide I/O scheme. It will stack memory on a logic controller and will connect them using TSVs. Wide I/O-2 will consist of four channels per die, x64 I/Os per channel (25.6-GB/s) and x128 I/Os per channel (51.2-GB/s). However, the industry is still debating the other specifications, such as the number of banks, page sizes, AC/DC parameters, pad order, pin description, addressing and command protocols.

In theory, LPDDR4 will have a power efficiency of 1 Watt at 25.6-GB/s. In terms of power, Wide I/O-2 is expected to be 50% to 60% lower than LPDDR4, Choi said. “Efficiency of CPU frequency could be improved largely by active heat dissipation,” he said.

One question still lingers, though: What ever happened to the original Wide I/O technology? Surprisingly, memory vendors insist the original Wide I/O devices will soon hit the market. If or when Wide I/O appears, the niche-oriented parts will likely be single-die solutions using micro-bumps, and not TSVs.

In fact, when the industry originally pushed for Wide I/O in 2008, it underestimated the challenges in developing 3D technology. The industry still faces many of the same problems today. TSV technology remains immature. It’s unclear how to deal with the thermal issues, and 3D test and the overall supply chain are not yet ready for prime time.

Cost is still a problem, as well. An applications processor based on conventional package-on-package (PoP) technology may run $28 each. If the same device was configured with a Wide I/O scheme, it could cost about $50, according to some experts. The cost of the substrate, coupled with the TSV production process, “eliminates the product margins for consumer applications,” said Pol Marchal, director of R&D at IMEC’s India unit. In fact, the TSV creation process is 40% or more of the total cost for a 3D device, Marchal said.

Applied’s Kumar disagreed, saying that the industry has reduced the cost for the TSV creation process. Many blame high 3D chip costs on the temporary bonding/debonding, test and other process steps.

There are a number of process steps to make a 3D chip. In the via creation process alone, there are five main manufacturing steps: etch, chemical-vapor deposition (CVD), physical-vapor deposition (PVD), electroplating, and chemical mechanical polishing (CMP).

Two years ago, the overall manufacturing cost-of-ownership (COO) for making a 5μ x 50μ TSV was about $150, Kumar said. Today, the COO is about $50, he said. “I think it will continue to drop,” he added.

Sunil Patel, principal member of the technical staff for package technology at GlobalFoundries, recently summarized the situation. “There are many issues we need to work through, such as how do you handle thin wafers once they are shipped, how do you test them and ensure known good dies,” he said. “If those wafers are packaged, that’s not a problem. If they’re not, how do you ensure the known good die? Also, with memory, the key integration is logic plus memory. In that case, the co-design of different die comes into the picture.”