Modeling High-Performance Analog And RF Circuits In Nanometer-Scale CMOS

By Mick Tegethoff and David Lee
Today’s consumer, communication, and computer electronic devices have clocks, communication interfaces, and high-speed signal-conditioning circuits that operate at radio frequencies (RF). Providing price-competitive products often requires monolithic integration of these circuits in low-power nanometer-scale bulk CMOS silicon. This is a worst-case scenario for RF designers, who must battle a dramatic growth in the number of low-voltage and increasingly nonlinear devices that are subject to nanometer-scale physical effects. There is mounting evidence that these physical effects — most notably device noise, parasitics, and crosstalk — fundamentally limit RF circuit performance at 65nm and below.

RF simulation tools have not kept pace with these changing design requirements.
Traditional RF simulators have severely limited capacity, have inherently limited accuracy, and trade off accuracy for performance. Although these tools are adequate for circuits down to perhaps 0.18 micron or 0.13 micron, they simply cannot provide accurate analysis at the nanometer scale. Lacking dramatically better tool capabilities, designers must rely on approximations that inevitably lead to silicon respins or overdesign (excessive area or power) — both of which are prohibitively expensive.

Nanometer-Scale RF Circuit Design Challenges
Designers of high-performance analog and RF circuits in nanometer-scale CMOS face a number of qualitative and quantitative challenges that did not exist just a few years ago.
Driven by requirements for increasing functionality and performance at decreasing cost and power, designers have rapidly moved to highly-integrated, low-voltage, bulk CMOS implementations — an environment that is fundamentally “hostile” to RF circuits. Low voltages mean dramatically less signal headroom and reduced linearity. At the same time, increasing signal bit resolution reduces quantization noise and unmasks thermal and flicker device noise effects. Device noise effects are growing significantly as a percentage of overall signal levels and fundamentally limit overall circuit performance at 45nm and below.

Designers are fighting signal-to-noise challenges by using more sophisticated circuit architectures, which inevitably increases overall complexity. In the case of mixed-signal interfaces, this includes using circuits such as charge pumps, switched-capacitor filters, phase frequency detectors, and dividers that produce sharp signal transitions. Interface blocks operating at multi-gigahertz frequencies are increasingly plagued by parasitics, which often outnumber pre-layout devices by 10x to 100x at nanometer technologies.

Behaving as noise sources and attenuators, these parasitics introduce extremely complex and often unpredictable signal effects that cannot be adequately estimated. Moreover, at these frequencies and signal levels, design teams can no longer rely on simple package models.
In addition to parasitic and package issues, the increasing variability in nanometer-scale processes impacts circuit performance characteristics and must be taken into consideration during block optimization. The increasing variation in circuit performance relative to specified operating ranges and tight implementation constraints (such as device mismatch) requires ever more intensive characterization through extensive corners and Monte Carlo analysis. However, these computationally intensive analyses are often impractical with traditional RF tools.

Silicon-Accurate Analysis
Given the rigorous demands of nanometer-scale GHz CMOS RF circuits, it is imperative that design teams have access to simulation tools that deliver silicon-accurate analysis.
Device models are the most obvious accuracy limitation and set the floor for overall analysis accuracy. All tool inaccuracies strictly add to this accuracy floor, thereby directly increasing design margin or the risk of silicon iterations. There are direct and indirect simulator inaccuracies.

Direct simulator inaccuracy includes the simulator noise floor and analysis-specific simplifications. Traditional SPICE transient provides a clear accuracy benchmark for time-domain analyses. Although often overlooked, indirect inaccuracies due to simulator capacity and performance limitations are even more critical. Increasingly designers cannot run sufficient analyses — or perhaps run a desired analysis at all — without using a divide-and-conquer approach, simplifying their circuit, modeling portions behaviorally, ignoring physical effects, or using a combination of these techniques. The only way to compensate for traditional RF simulator capacity and performance shortcomings is, again, through additional design margin or potential silicon iterations.

To learn more about modeling high-performance analog and RF circuits in nanometer-scale CMOS and Mentor’s Analog FastSPICE RF, click here.