Increasing heterogeneous integration means greater need for system-level analysis.
San Diego recently hosted the 54th International Symposium on Microelectronics. That’s a very generic title, so you should know that it is run by iMAPS, the International Microelectronics Assembly and Packaging Society. Generally, the conference is just known as iMAPS. One of the keynotes was given by Cadence’s KT Moore (in person). His presentation was titled “More Moore or More than Moore: an EDA Perspective.” Since KT’s last name is Moore, that’s probably enough Moores and we don’t really need more.
Of course, “more than Moore” is the catchy phrase used to describe other ways of scaling systems beyond purely dimensional scaling of the silicon, which is basically what Moore’s Law is all about. More than Moore is all about advanced packaging.
When KT heard about 7nm, he forecast that there might only be ten companies who could afford to do design at that node (I was skeptical that there would be a lot of design starts too, along with almost anyone else who made a prediction). We were all wrong. Several hundred companies are doing design at 7nm and below, between well-established semiconductor companies, startups throughout the world, and system companies moving into designing their own chips.
As you can see on the graph, advanced node growth is much higher than mature nodes (from a smaller base in terms of design starts, of course). But both are growing and the semiconductor industry is healthy.
There has been a bifurcation in complex system design, a sort of “Tale of Two Cities.” In the lower right of the diagram is traditional SoC, cramming everything onto a single die. In the upper left is the systems with photonics, RF, and so on. But they are starting to blend onto the line up the middle with heterogeneous system integration.
In 1985, KT graduated and went to work in the defense group at Texas Instruments. He was working on what was the largest design TI had done, with 9,000 transistors. Now you can have a single I/O on a chip that has that many devices. But in that era, the only thing you really cared about was “is it functionally correct?” Gradually we needed to check additional aspects of the design. Now in the More than Moore era, we are worried about how we get the system-level checks done at the same time. In EDA, we are no longer just concerned with what happens inside the IO-ring, but also what is happening outside the IO-ring.
In the system space, many aspects of the design have been independent, in their own silos. But lack of integration causes costly overdesign of individual die and packages.
The solution to lack of integration is obviously more integration. The image about shows the primary integration of Cadence tools for “planes, trains, and automobiles” which all have electronics…but also lots of other things. It is not just about the chips “inside the IO-ring,” but everything else outside, from electrical and thermal analysis to computational fluid dynamics.
Whereas once you might have analyzed a board, now you can analyze the whole system, and with reasonable compute. Because we are architecting this efficiently, you don’t have to have terabytes of memory, you can use standard hardware that is available to you in the cloud, either on-premises or off-premises.
Today, we use “More than Moore” to mean heterogeneous integration, but in fact this is an area where Cadence has been working for since the early 90s, since we talked about “multi-chip modules” or “MCMs.” Of course, this was long before Moore’s Law started to run out of steam.
One challenge every company faces is whether to build a product internally (sometimes called “organic”) or whether to acquire a company with expertise in an area. In the last two years, Cadence has built up a portfolio of products in the system space with a mixture of these two approaches. Since I normally write a blog post on any new product announcement and any new acquisition, I’ve added links to my coverage of each of these new capabilities.
One thing that even people in the industry are surprised about is that Cadence invests 38% of revenue in R&D. There are always new requirements in semiconductor design and integration.
KT wrapped up by talking about Integrity 3D-IC, a new product specifically aimed at designing 3D chips with stacked die. It handles 3D planning (what would be called floorplanning if it was all on one level) and implementation. It then performs early 3D thermal, power, and timing analysis. These capabilities combine together to allow optimization of PPA not just at the level of individual die but at the level of the system.
PPA is power, performance, and area, which is kind of a semiconductor thing. We talk about making the chips as small as possible, with as little power as possible, while achieving the best performance. The question is “how is that different for an advanced package?” It’s really not, but you have to take a different approach.
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At the end of the day, Integrity is what it’s all about. You want to know that you can build this thing with confidence. There’re a lot of places to miss things when you start combining these heterogeneous designs. So Integrity takes into account our place and route technology, our analysis technology. I believe we are the only company that can claim this is all integrated right now. So I’m going to claim it and say it’s true. This is where EDA is going and we are leading the charge with some of our customers and partners.
KT’s final question was the title of his keynote: More Moore or More than Moore?
And you won’t be surprised that KT’s answer was both.
The keynote itself is 40 minutes, and there are then 15 minutes of Q&A. So get yourself a coffee.
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