What is MRAM and why is it becoming more attractive to the industry?
By Dr. Meng Zhu, Dr. Roman Sappey, and Jeff Barnum
MRAM (Magnetoresistive Random-Access Memory) is a type of non-volatile memory (NVM) that utilizes magnetic states to store information. The basic structure of MRAM is a magnetic-tunnel junction (MTJ), which consists of two ferromagnetic (FM) layers separated by an insulating tunnel barrier (Fig.1). When the magnetizations of the two magnetic layers are parallel, the electrons tunnel easily across the barrier from one magnetic layer to the other, giving a low resistance state (RP). However, when the two magnetic layers are anti-parallel, the electron tunneling becomes difficult causing a higher resistance state (RAP). One of the most important parameters of an MTJ is tunneling magnetoresistance (TMR), which quantifies how well we can differentiate high and low resistance states. By manipulating the magnetization of one of the layers, information can be stored as “1” (high-R state) and “0” (low-R state) in the junction and then the information can be read by measuring the junction resistance. Changing the layer’s magnetization direction can be achieved by applying an external field, or by pulsing an electric current through the junction. The latter uses an effect called “spin-transfer-torque (STT)” to change the magnetization by polarized electrons.
Fig. 1 Basic structure of an MTJ when two ferromagnetic (FM) layers are in parallel and anti-parallel configurations. (Image: KLA Corporation)
STT-MRAM offers excellent scaling capability and friendly integration into current chip fabrication processes. Unlike DRAM, which needs to be continuously refreshed, STT-MRAM stores information without drawing power. Replacing DRAM with MRAM could prevent data loss and enable computers to start instantly without waiting for software to boot up. STT-MRAM has higher density than SRAM, and superior read/write speed over flash, with much higher endurance. All these merits make STT-RAM an attractive candidate to replace existing memories in certain applications, and perhaps eventually to become a universal memory solution.
Fig.2 shows the memory hierarchy in the Integrated Circuit (IC) industry. The horizontal axis represents the volume (capacity) of the memory/storage devices and the vertical axis represents the speed of the memory devices. In the past, there was a speed gap between the cache memory and the main memory, and between the main memory and the storage devices. Today, many emerging non-volatile memories (NVM) have started to close these gaps. Phase change memory (PCM), resistive random-access memory (RRAM) and MRAM are already in use as embedded NVM in some applications, such as microcontroller unit (MCU). In the next few years, MRAM may be able to replace some SRAM for cache memory, closer to the core processor. In the long run, MRAM, along with PCM or RRAM, are forecast to be able to serve as storage class memory solutions once their density can be further improved.
Fig. 2 Memory hierarchy in computation devices, past and current / future. (Image: KLA Corporation)
What are some of the end-use applications for MRAM products? Who are the key manufacturers? And what are market projections going forward?
Today’s STT-MRAM is gaining adoption for embedded memory applications to replace flash, EEPROM and SRAM. Several logic IDM/foundries are offering embedded STT-MRAM solutions: tsmc1 (22nm ULL CMOS), Samsung2 (28nm FD-SOI), GLOBALFOUNDRIES3 (22nm FD-SOI), Intel4 (22nm finFET). In the near future, we see embedded STT-MRAM (eMRAM) emerging in applications, such as the Internet of Things (IoT), microcontroller units (MCUs), automotive, edge computing and Artificial Intelligence (AI). Everspin Technologies5 is also offering several standalone MRAM products that are used in a wide variety of applications, including aerospace, automotive, storage, factory automation, IoT, smart energy, medical and industrial machine control / computing.
From a market perspective, although NAND and DRAM will maintain dominant positions over the next several years, MRAM is forecasted to grow significantly. By 2024, Yole Développement has reported the STT-MRAM market potential growth to be $1.8B ($1.2B embedded plus roughly $0.6B stand-alone), an 85% CAGR (2018-2024) with a total wafer production volume of >300K, a 126% CAGR (2018-2024) (Fig.3) 6
Fig. 3 MRAM market evolution by Yole Développement (Image: Yole MRAM Technology and Business 2019 Report) 6
How is an MRAM device fabricated? What are the key process steps and some of the specific process control challenges in the fabrication of MRAM?
MRAM devices are typically fabricated in the back end of line (BEOL) processes of the semiconductor fab. The key process steps are:
(1) Bottom electrode formation (Fig.4): The bottom electrode layer, formed by conventional patterning and damascene processing, needs to be polished to achieve planarization and to provide an ultra-smooth surface for MTJ stack deposition. Measuring and controlling the smoothness of the bottom electrode is critical to the device performance. Final height of the metal electrode must be controlled and monitored. It must also be defect free.
Fig. 4 Illustration of bottom electrode (BE) formation (Image: KLA Corporation)
(2) MTJ stack deposition (Fig.5): MRAM is formed by precisely depositing at 20 to 30 different metal and insulating layers, each typically being between 0.2 and 5.0nm thick, using a single, integrated physical vapor deposition (PVD) cluster tool. Each layer must be precisely measured and controlled for thickness, uniformity, roughness and stoichiometry. A magnesium oxide (MgO) film is the core of the magnetic tunnel junction (MTJ), the critical layer that forms the barrier between the free layer and reference layer. It needs to be deposited with 0.01nm precision to repeatedly achieve the targeted resistance-area product (RA) and tunnel magnetoresistance (TMR) characteristics. RA and TMR are critical parameters that dictate device performance, yield and reliability. Even a few missing atoms can significantly affect RA and TMR, which explains why metrology is so critical in MRAM manufacturing.
Fig. 5 Illustration of a generic example of MRAM stack deposition (Image: KLA Corporation)
(3) Magnetic annealing: Annealing of the stack post deposition sets the crystal orientation of the reference layer (interface below MgO) and the MgO tunnel barrier. Typically, the MTJ is annealed at elevated temperature in a magnetic field to improve the materials and interface quality and to set the magnetization orientation. Both electrical and magnetic properties of the MTJ need to be monitored after this step for process control. These are key inline metrology steps for MRAM fabrication.
(4) Patterning MTJ pillars (Fig.6): MRAM cells are typically circularly-shaped pillars on the order of 20-100nm diameter. The pattern transfers from mask to photoresist, and from photoresist to MTJ stack need to be controlled precisely for the devices to work. Lithography overlay patterning alignment through a non-transparent MTJ stack is a challenge. Ion beam etching of the pillars must be completed without damage and without metallic redeposition on the MTJ sidewall while stopping on the bottom electrode. Etch corrosion, damage, and metal re-deposition along the MgO exposed layer are key issues which must be monitored during this step. Monitoring and controlling the final MTJ pillar height and shape – primarily at the MgO interface – and the pillar diameter are crucial to achieving uniform cell patterning, which in turn, minimizes the switching distribution of MRAM cells. Finally, an encapsulation layer covers everything to protect the MTJ device. This layer must be defect free with a thickness that meets required specifications.
Fig. 6 Illustration of an etched MRAM pillar (before encapsulation layer) (Image: KLA Corporation)
(5) Top electrode formation: The top electrode is formed much like the bottom electrode, with pattern alignment being key. Using a dual damascene process, CD, shape, profile and depth are also important in the final structure, as well as any type of defectivity.
What is KLA doing to enable the success of MRAM?
KLA is excited about the forecast for MRAM as an up and coming NVM technology. As a process control and process-enabling technology leader, we provide IC manufacturers with a portfolio of solutions that help accelerate MRAM product development ensure a successful ramp and drive maximum yield in production. Specific technology solutions that we offer for MRAM include:
For more information, please visit www.kla.com, or contact your local KLA representative.
References:
Meng Zhu is a product marketing manager at KLA.
Roman Sappey is a senior technologist for SensArray & MRAM Metrology at KLA.
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