Multiple Patterns, Multiple Trade-Offs

A deep dive into what you expect to encounter and what you’ll really find in multi-patterning at advanced process nodes.


As the saying goes, “There is no such thing as a free lunch.” That is a reality that chip designers have had to live by from the beginning. From the advent of the first design rule, it was clear that you couldn’t just do anything you wanted.

In the end, everything comes down to trade-offs. Whether it’s area, speed, leakage, noise sensitivity, or drive current, doing something to improve one metric always seems to lead to degradation of another metric. And these trade-offs don’t just exist at the high-level chip metrics. At the core of physical design, almost every design rule interacts with many other design rules. Make the simplest change to fix one design rule violation, and you seem to get a fail in one of the other rules. The art of design is finding that sweet spot that complies with all the rules and still provides the needed circuit functionality and performance. The move to multi-patterning processing in manufacturing inevitably led to new design restrictions, and thus new trade-offs.

I want to discuss a few of the trade-offs that are unique to multi-patterning. Some may be obvious, but others are probably not. Most of them are trade-offs being made in real time at a given step in the design flow, but some of them interact across various points in the design flow, which means they can surprise you if you aren’t considering them throughout the design flow.

Let’s start with the most obvious trade-off: area. Multi-patterning introduces additional spacing constraints. Unlike single patterning, where there is a single version of each minimum spacing constraint, in a multi-patterned process there are two versions of each minimum spacing constraint. There is a process minimum space constraint for polygons on different masks, but a different (and usually larger) minimum space constraint for polygons on the same mask.

Figure 1 demonstrates this basic rule doubling of spacing requirements.

Figure 1: Comparison of minimum spacing rules in single vs multi-patterned designs.

These additional spacing requirements increase the likelihood that a given multi-patterned circuit implementation will require larger area trade-offs compared to single mask designs. In other words, it is unlikely that you could simply convert an existing single mask design to a multi-patterned design node without making layout modifications that end up increasing the relative design area.

There are other DRC rules impacted by multi-patterning that you might not think of right away. Traditionally, you must meet certain density constraints in the layout. It is usually measured across the whole chip, and in windowed regions, stepped across the design to make sure you meet a certain minimum density of layout in each window and that density is fairly uniform across the chip. If you are coloring your layout to send it to a foundry, then you must also comply with new density balancing rules that ensure you have a relatively uniform density distribution between the colors in each window. At first glance, you might think that if you meet the basic density constraints and that most polygons alternate color, then you would naturally have a good balance between the two colors. However, there are many situations where this is not necessarily true (Figure 2).

Figure 2: Density balancing in multi-patterned layouts can be challenging.

In analog layouts in particular, there may be very large polygons as shown on the left. Such polygons could cover most, if not all, of a window region being checked. Because there is a single polygon, it must be a single color, which would lead to a very biased color ratio in that window. Similarly, if neighboring polygons alternate, but the neighbors have very different areas (sizes), then this leads to regions of very biased color ratios, as shown on the right. So, there are trade-offs between the types of multi-patterning constructs you can draw and still meet density requirements.

You also may have to make trade-offs between hierarchy and density balance. Good hierarchy (lots of placements of the same cell) makes for a much smaller database size, and better runtimes in most EDA tools. However, when coloring is involved, you can only maintain the hierarchy of a cell if all placements of that cell have the same coloring. Figure 3 illustrates the trade-off between keeping hierarchy and improving density balancing.

Figure 3: Hierarchy vs. density balancing trade-offs.

In this example, there are two cells represented in a layout. Both are placed in the top cell. But Cell_B is placed repeatedly on top of Cell_A, as shown. The spacing between the polygons in Cell_A is wide enough that the polygons could be placed on any mask colors. So, for the sake of density balancing, it would be helpful to alternate them between the two colors. However, because Cell_B is placed six times (once on each polygon in Cell_A), you cannot alternate the colors and must flatten Cell_B. To keep Cell_B intact, all placements must be the same color. You must sacrifice the color alternation to keep the hierarchy, or vice-versa.

Density balancing even needs to be considered when defining your basic standard cell library architecture. Consider the impact of a simple choice between an even and odd number track library architecture, as demonstrated in Figure 4. Given the odd track library at top, the color alternation will always force the power and ground rails to be different colors. The area of the power rails is typically very large compared to the area of the routing tracks between them, but since they alternate, you end up with fairly balanced colors. With the even track example at the bottom, the color alternation forces the power and ground rails to be the same color. This builds in a significant imbalance between the colors in the standard cell portion of the design.

Figure 4: Standard cell library architecture can affect density balancing when multi-patterning is required.

If this innate imbalance is too significant (depending on the ratio of power rail size to routing track size, for instance), it may not be possible to use even track libraries. Figure 5 shows a real life example of the kind of impact this could have. On the left is a histogram of the density window color ratios, a map of the same density windows over the layout, and a close-up of the metal layout inside one of those windows. You can see that the histogram bars are all shifted to the right of 50%, with the average ratio of color1 being 67.26%. On the right is the density ratio distribution of the layout when ignoring the power rails. You can see that this data is centered on 50%. Forcing the power rails to be the same color significantly biases the density balance ratios.

Figure 5: Density balancing window distributions, given same standard cells that force the same color on power and ground rails.

Moving to 10nm and below, nodes will see the introduction of triple (TP) and quadruple (QP) processes on some layers. Unlike double patterning (DP), the computational complexity of TP and QP from a pure computer science algorithmic standpoint requires exponentially longer runtimes as a function of the number of polygons processed. The computer scientists refer to this as NP Complete or NP Hard, which makes a great read in Wikipedia. However, it doesn’t make for a practical EDA design solution. The answer is to constrain the complexity of the layout so that more runtime-efficient heuristic algorithms can check or decompose the layout into three or four colors. Additional design rules and design methodology constraints will be required to try and limit the potential complexity of the data that needs processing. Again, this will probably come as a trade-off to area density.

You also may encounter special new checks solely targeted at making sure the complexity of any particular portion of a layout is limited such that the checking and coloring algorithms can be assured of finding a solution in a reasonable runtime. Think of the complexity limit as a knob for trading off runtime against the amount of complexity that can be robustly processed. Figure 6 shows an example of a TP complexity error. The lines on the right represent the spacing constraints that require the colors to alternate between the various polygons. The red sub-component of the data exceeds the complexity limit for the specified run.

Figure 6: Complexity check error in TP.

Note that failing this check does NOT mean the data is or is not colorable. It simply means that an answer to whether or not it can be colored and providing a verified colored solution is not determinable within the set runtime limit. Since runtime is essentially exponential with the level of complexity, you can’t just arbitrarily increase the limit. The designer must instead decrease the complexity of this portion of the layout by breaking some of the spacing interactions between the polygons. A couple of the separators on the right are circled in black. If these separator spacing locations are broken (moved apart), the effect could dramatically change the component, in the sense that it would break large circular interactions within the component, and may reduce the complexity enough to satisfy the heuristics.

Finally, multi-patterning trade-offs extend beyond the physical constraints to the electrical constraints. Since traditional DP, TP, and QP use multiple photo steps to print the various masks, each imaging step may misalign relative to the target, and thus relative to each other. This misalignment introduces a new source of capacitive variation in the layout between the polygons on the same metal layer. In Figure 7, we see an example of how DP masks can misalign, and how new parasitic extraction (PEX) corners may need to be considered to calculate accurate timing margins.

Figure 7: DP misalignment may create additional PEX corners to consider.

At 10nm and below, you may encounter even more exotic types of multi-patterning. Self-Aligned Double Patterning (SADP), for instance, has an advantage over traditional litho-etch-litho-etch (LELE) DP in that the two patterns do not misalign relative to each other. That sounds great, but again, there is a trade-off. Because of the deposition and etch steps involved in this type of process, the critical dimension (CD) bias of one of the patterns may be significantly more variable than the other. So polygons in your circuit that are one color will have more PEX variability than polygons assigned to the other color. You may find yourself trying to manipulate particular critical net polygons to specific colors to minimize variability. Of course, trying to force more polygons to a particular color runs in the face of spacing and density balancing constraints. Remember, “There is no such thing as a free lunch!”

In my next blog, I want to dig deeper into this whole topic of density balancing. It is a complex subject affected by many different aspects of design and manufacturing. In the meantime, I’m going to lunch…who’s buying?