New 3D Stacking Techniques Emerge

Alternatives to through-silicon vias and water cooling of die under development to ease transition.

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By Pallab Chatterjee
To take advantage of the capabilities of the new technologies, design and circuit architectures in the future will have to be closely coupled with the basic device creation.

That shift was the subject of a special session at the recent IEDM conference focusing on the confluence of technology and design. One such area under discussion involved 3D ICs. While a lot of discussion has taken place about the use through-silicon vias (TSVs) for connecting stacked die, this technology is still in its early stages for reliability and design rules. TSVs require additional process steps beyond the standard wafer processing and they have to be spaced away from active circuitry on all sides. The comparatively large size (typically 5um x 5um or larger) on a small process (40nm node), for a size factor of 125x, created a complete blockage of all routing from the bottom of the TSV to the top of the chip and has impact on design closure. As there is mechanical compression from the bonds on the TSV to the adjacent die, the TSV cannot be located over all types of circuitry without affecting device operation.

A solution to these issues is the use of a design technique called through-circuit interconnect (TCI), which is a low power RF solution that does not require any additional processing steps. The technique uses small-field RF antennas that are approx 100um/side and which are connected by standard high-speed transceivers. The technique has the advantage of being compatible with low-power processes as the data transfer energy is only 0.01pJ/bit and can communicate to multiple die in a multi-die stack. The data transfer has been tested at 11Gb/s/ch and can be aggregated to 8Tb/s over 1000 channels in only 6.4mm-sq. The inductive coupling technique supports a reliability BER<10-14 and a cost reduction of more than 20 cents per chip. Moreover, the technique has been in development and has presented results since 2004.

One of the performance and reliability issues for 3D stacked ICs is the thermal handling of the die. In a normal single-die arrangement there is direct uniform contact between the die and the package, which can have a variety of heat dissipation techniques used to cool the part. In a stacked-die scenario there is a localized thermal issue in the areas the die overlap. A technique was shown that uses inter-tier microchannels etched in the bulk side of the die for pumping a cooling fluid. The technique is very effective, but work is needed to optimize the flow rate control of the micro-pumps in the system to reduce their energy use, and balance the flow rates to the dynamic thermal loads. The preliminary results have shown a 21% improvement in system-level energy vs. air cooling.

On the circuit side, there are changes in the basic P and N devices. New processes have advanced features such as strain engineering, high-K dielectrics, and novel channel materials & device structures. Traditional devices have performance optimization based on pre-determined Vdd and Ioff levels. However, these new devices have power and performance constraints that require simultaneous optimization of Vdd, Ioff, Lg, Tox, and other parameters. Applications such as SRAMs have different noise margins per device with new processes, and as a result the devices have process technology variability sensitivity and a strong sensitivity to the use in circuits and the device configuration.