NoC Straight Talk

The increase in SoC complexity has a direct correlation to the increased interest in on-chip networks.


Increased interest in on-chip network IP is without a doubt directly correlated to the increase in SoC complexity and performance over the past few years. Some SoC design managers even have gone so far as to say that the success of their SoC program is directly related to their ability to implement an on-chip communications network. Underestimating the importance of the on-chip network has caused many SoC programs to miss their performance targets, schedules, or even be canceled altogether.

Why? The on-chip network touches most aspects of the design, from early SoC architecture exploration all the way through to back-end layout. This includes interface protocol support (e.g. AMBA, OCP, PIF, etc.), performance, memory scheduling, quality-of-service, power management, security, system domain partitioning, verification and more. Get any one of these wrong in the SoC design and you will have a chip that either underperforms or, even worse, one that does not work at all.

What’s so special about a NoC and how does it help SoC design teams deal with all this complexity? Unfortunately, before answering the question, I need to discuss terminology. Discussing terminology in this case is not simply an academic exercise, but essential for getting to the root of the question. A NoC typically refers to a specific network topology implementation using links and routers to form connections between IP cores. A NoC also is characterized by packetizing and serializing the data (i.e. the networking analogy). When using the term NoC, there is potential for confusion because some understand it to only mean the process of packetizing/serializing the data, while others mean the entire on-chip communications network. The implementation of a NoC also varies with some using simple muxes/demuxes with retiming for the topology structure, while others implement actual routers.

Now to answer the specific question, a NoC is an important part of the overall on-chip communications network because it provides scalability, allowing the network to expand without adding complexity. It also reduces wiring congestion and allows higher performance due to the packetization and serialization. The topology structure also should facilitate easy system partitioning so that IP cores can operate in their own power, voltage and frequency domains. Clearly, these capabilities are very important in large scale SoCs, where complex designs have tens of power domains and many tens of clock domains.

In addition to the NoC, there are other types of fabric that play a key role in the SoC system design. Peripheral interconnects, for example, are much more gate-efficient when connecting low-performance cores. Complex SoCs also have subsystems that require very high-speed low-latency connections. These interfaces are better suited for parallel connections (i.e. no packetization or serialization). These other fabric types can combine with the NoC to give the SoC designer a complete ‘toolbox’ of choices to ensure the most optimal network topology structure.

What about the rest of the network? In addition to the NoC, there are other key components needed that are independent of the fabric choice. One major component is the network interface to the IP cores in the system. These interface blocks are critical because they isolate the cores from the network, do the protocol conversion, bit conversion and work with the fabric on advanced services such as QoS, security, error management and power management. Isolating cores from the network is valuable because it facilitates IP core reuse, and allows modifications to the SoC without affecting the rest of the chip. This provides scalability from one SoC design to the next.

Ultimately, what the SoC designer needs is a complete solution for their on-chip communications network. This solution must contain all the necessary on-chip network IP components, verification IP, support for back-end layout and timing closure. They need choices for their fabric topology that will provide the best system performance at the most efficient gate count. The solution must also include design tools that provide system capture and performance analysis so that the network can be optimized. Clearly, a NoC is an important of part this solution, especially when coupled with all the other network IP components. And that’s the straight talk on NoCs.

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