tag: Nvidia

Software-Hardware Co-Design Becomes Real
By Brian Bailey - 27 Sep, 2021 - Comments: 1

For the past 20 years, the industry has sought to deploy hardware/software co-design concepts. While it is making progress, software/hardware co-design appears to have a much brighter future. In order to understand the distinction between the two approaches, it is important to define some of the basics. Hardware/software co-design is essentially a bottom-up process, where hardware is deve... » read more

Building Complex Chips That Last Longer
By Ed Sperling - 23 Sep, 2021 - Comments: 0

Semiconductor Engineering sat down to talk about design challenges in advanced packages and nodes with John Lee, vice president and general manager for semiconductors at Ansys; Shankar Krishnamoorthy, general manager of Synopsys' Design Group; Simon Burke, distinguished engineer at Xilinx; and Andrew Kahng, professor of CSE and ECE at UC San Diego. This discussion was held at the Ansys IDEAS co... » read more

Data Tsunami Pushes Boundaries Of IC Interconnects
By Ann Mutschler - 22 Sep, 2021 - Comments: 0

Rapid increases in machine-generated data are fueling demand for higher-performance multi-core computing, forcing design teams to rethink the movement of data on-chip, off-chip, and between chips in a package. In the past, this was largely handled by the on-chip interconnects, which often were a secondary consideration in the design. But with the rising volumes of data in markets ranging fro... » read more

Blog Review: Sept. 22
By Jesse Allen - 22 Sep, 2021 - Comments: 0

Ansys' Tyler Ferris describes some of the many ways electronics on a PCB assembly can fail, from component level failures like wirebond breaking and liftoff to board-level failures such as conductive anodic filament failure. Cadence's Paul McLellan considers the switch from low-speed parallel interfaces to high-speed serial interfaces as one of the key advancements making modern data centers... » read more

RISC-V Processor Verification: Case Study
By Imperas - 22 Sep, 2021 - Comments: 0

Abstract: The open RISC-V instruction set architecture is gaining traction with both semiconductor vendors and systems companies. A key question is how to verify the RISC-V processor implementation, especially when developing the RTL and/or adding custom instructions? This paper reports on the techniques used and lessons learned for the verification of a RV64IMACBNSU RISC-V processor by an exp... » read more

Blog Review: Sept. 8
By Jesse Allen - 08 Sep, 2021 - Comments: 0

Synopsys' Scott Durrant considers the IP used in HPC SoCs and the efforts to simultaneously minimize data movement and maximize the speed at which data is transferred from one location to another, whether that data transfer is across long distances or from one chip to another within a server. Cadence's Paul McLellan looks into a new version of the Rowhammer DRAM vulnerability that can allow ... » read more

Week In Review: Design, Low Power
By Jesse Allen - 27 Aug, 2021 - Comments: 0

The UK's Competition and Markets Authority is raising new challenges for Nvidia's proposed acquisition of Arm, suggesting in a new report that an in-depth Phase 2 investigation into the deal is warranted on competition grounds. Andrea Coscelli, chief executive of the CMA, said, “We’re concerned that Nvidia controlling Arm could create real problems for Nvidia's rivals by limiting their acce... » read more

Week In Review: Auto, Security, Pervasive Computing
By SE Staff - 20 Aug, 2021 - Comments: 0

Security Infineon Technologies is coordinating a group of twelve partners, including researchers, electronics industry, and end users, who are working to find and fix IoT security flaws. The research project, called “Design methods and hardware/software co-verification for the unique identifiability of electronic components” falls under VE-VIDES, which is part of the Trustworthy Electronic... » read more

Has Computational Storage Finally Arrived?
By Andy Patrizio - 11 Aug, 2021 - Comments: 2

The idea behind computational storage is not new. It’s just that like so many concepts, the idea has been well ahead of the technology. In a nutshell, computational storage brings processing power to the storage level. It eliminates the need to load data from the storage system into memory for processing. Moving data between storage and compute resources is inefficient and computational sy... » read more

Blog Review: Aug. 11
By Jesse Allen - 11 Aug, 2021 - Comments: 0

Arm's Rahul Mathur finds that traditional interconnects have become a bottleneck for improving IC performance and suggests buried interconnects as a way to lower signal routing delay. Cadence's Paul McLellan checks out forksheet FETs, a new transistor type that could allow scaling past 3nm, and the interconnect advances that will need to accompany it. A Synopsys writer explains the new LP... » read more

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