tag: EDA

Week 47: The Yin And Yang of DAC
By Anne Cirkel - 01 May, 2015 - Comments: 0

In one of my early blog posts I explained that DAC is owned by three non-profit societies: ACM, IEEE/CEDA and EDAC. While the executive committee right now is working on a successful 52nd DAC, planning for future events has already started. Future locations are usually booked years in advance as most of convention center and hotel contracts are signed at least 18 months out. The financial liabi... » read more

Problems Ahead For EDA
By Brian Bailey - 27 Apr, 2015 - Comments: 0

You may have discovered that the Semiconductor Engineering Knowledge Center (KC) provides various ways in which data can be viewed. One way is to see what events happened in a given year. During the 1990s, company activity in terms of new startups and acquisitions reached a peak, and in 1997 there were at least 29 startups that the KC contains and 25 companies acquired (let us know if there wer... » read more

Week 46: Don’t Be Late
By Anne Cirkel - 24 Apr, 2015 - Comments: 0

Last year we moved DAC’s official opening session from Tuesday to Monday. The move makes perfect sense as there is much on the Monday schedule, including tutorials as well as the designer and IP track sessions. The opening session has always been special at DAC. It is the most popular general session as various awards are given out that day too. This is how it works: Throughout the year A... » read more

Moore’s Law At 50
By Ed Sperling - 23 Apr, 2015 - Comments: 0

Moore's Law turned 50 this week…but not because of Gordon Moore. He observed that the number of transistors crammed onto a piece of silicon was doubling every 18 to 24 months and predicted that would continue to be the case. He was right, but it took many thousands of engineers who created methodologies and tools to automate the design and equipment to manufacture complex chips to make that o... » read more

Is Art Acceptable In Verification?
By Brian Bailey - 23 Apr, 2015 - Comments: 0

The industry appears to have accepted that [getkc id="10" kc_name="verification"] involves art as well as science. This is usually based on one of three reasons, namely: the problem is large and complex; there is a lack of understanding and tools that enable it to be automated; and if it could be made a science, all of the jobs would have migrated offshore. Today, designs are built from pre-... » read more

Pressure Builds To Revamp The Design Flow
By Ed Sperling - 23 Apr, 2015 - Comments: 1

Without [getkc id="7" kc_name="EDA"] there would be no [getkc id="74" comment="Moore's Law"] as we know it today, and without Moore's Law there would be a much more limited need for EDA. But after more than three decades of developing design flows packed with sophisticated tools to automate semiconductor design through verification, and thereby enable feature shrinks that are the basis of Moore... » read more

Less Moore Means More Intelligence
By Brian Bailey - 23 Apr, 2015 - Comments: 3

It would seem as if the entire industry is flooding the forums with articles about [getkc id="74" comment="Moore's Law"], as it reaches its 50th birthday (April 19th) and that this represents the longest and most important exponential in the history of man. The numbers and that impact are everywhere and I do not intend to repeat them. There are lots of articles talking about when Moore’s law ... » read more

Tech Talk: Virtual Prototyping
By Brian Bailey - 22 Apr, 2015 - Comments: 0

Bill Neifert, CTO of Carbon Design Systems, talks with about the intersection of IP and EDA, driven in particular by ARM's new architecture. [youtube vid=1OopYWmRarE] » read more

FD-SOI Vs. FinFETs
By Ed Sperling - 16 Apr, 2015 - Comments: 1

Semiconductor Engineering sat down to compare the benefits, risks and challenges of moving to finFETs compared with fully depleted silicon on insulator ([getkc id="220" kc_name="FD-SOI"]) with Philippe Magarshack, group vice president for technology R&D at [getentity id="22331" comment="STMicroelectronics"]; Marco Brambilla, director of engineering at [getentity id="22150" e_name="Synapse D... » read more

Faster Time To Root Cause With Diagnosis-Driven Yield Analysis
By Mentor, a Siemens Business - 16 Apr, 2015 - Comments: 0

ICs developed at advanced technology nodes of 65 nm and below exhibit an increased sensitivity to small manufacturing variations. New design-specific and feature-sensitive failure mechanisms are on the rise. Complex variability issues that involve interactions between process and layout features can mask systematic yield issues. Without improved yield analysis methods, time-to-volume is delayed... » read more

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