Executive Insight: Jack Harding


SE: What's changed over the past 12 months? Harding: My starting point these days is around consolidation. At last count there were about 85 companies in the semiconductor industry. My bet is that at this time next year there will be about 70. The size of deal will not matter. Nothing will be too big. The strategic question is whether you're playing musical chairs and when the music stops, ... » read more

Toward Smarter Design Automation


In less than two weeks, the EDA industry will convene for its biggest conference of the year, the Design Automation Conference, again in San Francisco. Last year, I “came clean” with a post called “Confessions Of An ESL-Aholic,” pointing out that beyond high-level synthesis, a significant shift towards a more abstract design description than RTL has not yet happened and that a lot of th... » read more

Tortuga Logic: Hardware Security


For the Internet of Things to really get rolling, it has to be bulletproof. And given the number of very high-profile security breaches in recent months, it has a long way to go before consumers or businesses will feel comfortable using any of a new wave of smart devices That concern has prompted a wave of acquisitions from companies such as Intel (McAffee), Cadence (Jasper Design Automation... » read more

Problems Ahead for EDA


Semiconductor Engineering sat down with [getperson id="11411" comment="Bill Neifert"], chief technology officer at [getentity id="22521" comment="Carbon Design Systems"]; [getperson id="11032" comment="Simon Davidmann”], chief executive officer for [getentity id="22036" e_name="Imperas”]; Randy Smith, vice president of marketing for [getentity id="22605" e_name="Sonics"] and Michel Courtoy,... » read more

Correct-By-Design Methodology Requires Carefully Defined Constraints


Since the dawn of PCB usage, constraints have been an important part of the design. What are the dimensions? What weight of copper? Now, constraints have become much more than just physical dimensions. The most important constraints are defined by the design requirements of differential pairs, BGAs, low voltage devices, and high-speed parallel interfaces. The cost of rework skyrockets the fu... » read more

The Roadmap To 5nm


By Debra Vogler Among the challenges the semiconductor industry will be facing as it moves down the path to node 5 are resistance-capacitance (RC) management and integration. SEMI is pleased to announce a SEMICON West 2015 STS technical program exploring these and other high-volume manufacturing challenges. According to An Steegen, SVP of Process Technology at imec, the list of RC managemen... » read more

Week 48: One Week Left For Early Registration


I have to admit, writing the weekly blog has made the countdown to DAC a lot more apparent than it would have been otherwise. When I began blogging last year, I thought the watched-pot-never-boils maxim might apply, that time would drag and I’d run out of things to say months before the opening keynote. Instead, I’m fairly stunned to have just four more blogs to write until “my DAC year�... » read more

How Semiconductor IP Became Critical To SoC Design


By Mark Templeton In 1991, I had the good fortune to be a member of the founding team of Artisan Components. We started the company believing that demand was about to appear for semiconductor intellectual property. We had a few data points. We knew that before a company could start a new chip project, they first had to design and verify all kinds of generic building blocks – things like ... » read more

Problems Ahead For EDA


Semiconductor Engineering sat down with [getperson id="11411" comment="Bill Neifert"], chief technology officer at [getentity id="22521" comment="Carbon Design Systems"]; [getperson id="11032" comment="Simon Davidmann”], chief executive officer for [getentity id="22036" e_name="Imperas”]; Randy Smith, vice president of marketing for [getentity id="22605" e_name="Sonics"] and Michel Courtoy,... » read more

Tech Talk: Faster SPICE


ProPlus CTO Bruce McGaughy explains why FastSPICE (fast Simulation Program with Integrated Circuit Emphasis) is running out of steam in the finFET generation and what needs to happen next. [youtube vid=07XzUQxPUr8] » read more

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