Patterning Interconnects At 10nm And Below

How to extend the TiN metal hard mask to future process nodes.


By Connie Duncan
Chip manufacturers today build billions of transistors on a chip, delivering incredible computing power to consumers. What often gets overlooked is how hard it’s getting to create the many miles of ultra-thin copper wiring used to connect each of the transistors. Patterning these electrical pathways is becoming increasingly challenging as they grow denser and finer, and any defect can impact the chip’s performance or render it useless.

Innovation in materials engineering technology for the hardmask is required to preserve the pattern integrity of the tightly packed, tiny interconnect circuitry. Applied’s Sree Kesapragada, global product manager, together with Miller Allen, director of BEOL PVD technology, discuss how to meet copper interconnect patterning needs by extending the TiN metal hardmask – the industry’s material of choice – to the 10nm and below nodes.

To view the video, click here.

Connie Duncan is manager of technical media relations at Applied Materials.

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