A new technical paper titled “Rethinking Programmed I/O for Fast Devices, Cheap Cores, and Coherent Interconnects” was published by researchers at ETH Zurich.
Abstract:
“Conventional wisdom holds that an efficient interface between an OS running on a CPU and a high-bandwidth I/O device should be based on Direct Memory Access (DMA), descriptor rings, and interrupts: DMA offloads transfers from the CPU, descriptor rings provide buffering and queuing, and interrupts facilitate asynchronous interaction between cores and device with a lightweight notification mechanism. In this paper we question this wisdom in the light of modern hardware and workloads, particularly in cloud servers. We argue that the assumptions that led to this model are obsolete, and in many use-cases use of programmed I/O, where the CPU explicitly transfers data and control information to and from a device via loads and stores, actually results in a more efficient system. We quantitatively demonstrate these advantages using three use-cases: fine-grained RPC-style invocation of functions on an accelerator, offloading of operators in a streaming dataflow engine, and a network interface targeting for serverless functions. Moreover, we show that while these advantages are significant over a modern PCIe peripheral bus, a truly cache-coherent interconnect offers significant additional efficiency gains.”
Find the technical paper here. September 2024.
Ruzhanskaia, Anastasiia, Pengcheng Xu, David Cock, and Timothy Roscoe. “Rethinking Programmed I/O for Fast Devices, Cheap Cores, and Coherent Interconnects.” arXiv preprint arXiv:2409.08141 (2024).
Leave a Reply