Power Integrity Analysis For High-Performance FPGAs

Predicting and preventing electromigration and IR drop effects in FPGA designs.


Efinix high-performance Titanium field-programmable gate arrays (FPGAs) are custom-tailored for the computing demands of mainstream applications, targeting markets from intelligent edge devices to industrial automation to vision systems to edge servers and communications (figure 1). Efinix customers use the Titanium line of FPGAs to ensure their complex, high-performance designs minimize power consumption within an aggressive transistor density goal. They must seamlessly integrate intellectual property (IP), such as microcontrollers, serial peripheral interfaces (SPI), or inter-integrated circuit controllers (I2C), within aggressively accelerated development cycles, while incorporating the latest in power consumption management techniques, and the resulting proliferation of physical rails and voltages.

Fig. 1: Titanium FPGA block diagram. (Source: Efinix. Used by permission.)

To ensure good power distribution, find and eliminate hotspots, and increase yield, Efinix must be able to quickly and accurately predict and prevent electromigration (EM) and voltage (IR) drop effects in their FPGA designs during the design and verification flow. Any power integrity analysis tool they use must be able to run accurately and efficiently throughout the design cycle, while also accommodating the increasing data sizes implied by each generation of Titanium products.

In the past, Efinix employed multiple EMIR analysis solutions, but each presented performance or capacity issues that reduced their efficiency and accuracy. Efinix typically ran EMIR on small-sized layouts using detailed standard parasitic format (DSPF)-based simulation, but this approach consumed too much runtime or memory above a certain size threshold. For larger designs, the design team would abstract the small blocks, then perform manual review of the full-chip rails against the design specifications. Not only was this process tedious, time-consuming, and prone to errors, but it was also difficult for engineers to determine if layout fixes were required. Although no serious problems escaped this review process, Efinix was forced to invest large quantities of engineering time in this process.

Even when using complex hierarchical modeling techniques, Efinix found that existing market solutions lacked the capacity and performance for analysis of the entire chip. Efinix engineers could not turn around results on all power rails in their Titanium FPGA designs in a timely manner without aggressive data reduction tricks and parceling of the job into multiple repetitive runs on multiple servers. The recommended CAD flows for these solutions required DSPF extraction, which is impossible for full-chip analysis, as well as adherence to a strict hierarchical digital design flow, which was precluded by the aggressive PPA goals for the Efinix Titanium products.

The introduction last year of the mPower power integrity analysis platform from Siemens EDA changed all that. The mPower platform provides power integrity verification for digital, analog, and 3D IC designs across all design flows, at any scale. Analog, semi-custom and digital power integrity analysis can be readily integrated into existing design flows while scaling to circuits and chips of any size. In particular, the mPower Analog tool provides scalability previously only available in the digital domain to transistor-level designs to enable static and dynamic analysis on the largest circuits.

The mPower cockpit offers high capacity, stability, and speed for loading and browsing of result maps. Report browsers offer diverse methods of filtering and sorting, with cross-probing to the mPower cockpit maps, as well as cross-probing to industry-standard design canvases and database viewers. Results mapping and reporting include current distribution, current density, EM violations, limiting resistive paths, effective resistance, power consumption, and IR drop.

Fig. 2: The mPower cockpit enables engineers to easily explore EMIR maps and cross-probe from reports to industry-standard layout tools. (Source: Siemens EDA)

The mPower flow also leverages industry-standard Calibre databases, interfaces, and collateral, easing setup and adoption while providing confidence in rule decks and parasitic extraction layer stacks that have been validated by leading foundry qualification efforts and repeated use across the industry. Leveraging the Calibre database directly eliminates reliance upon full-chip DSPF extraction, an impossibility for all but the smallest designs.

With the implementation of the mPower power integrity solution for 1st and 2nd generation devices in their Titanium FPGA product line, Efinix was able to accelerate their power rail engineering change order (ECO) process substantially. The mPower platform delivered full-chip static IR within 24 hours turnaround on existing servers equipped with 2TB of RAM, successfully analyzing several hundred million transistors where other solutions had previously failed. Efinix not only saved at least two weeks of data preparation and analysis on each rail layout iteration, but also identified violations that manual inspection would have missed. In addition, ongoing collaboration between Siemens and Efinix has enabled Siemens to subsequently deliver multiple factors of mPower performance and memory improvement to accommodate the multiplying demands of Efinix FPGA designs.

The Siemens mPower solution delivers power integrity analysis capacity and performance to the Efinix FPGA design teams, liberating them from cumbersome legacy flows that required prohibitive extraction, data preparation, manual review, and retrofitted, inappropriate digital IP methodologies. As the Efinix Titanium FPGA family continues to expand, providing larger, higher gate count devices to meet customer demands, and implementing more complex system-on-chip (SoC) architectures on more advanced process nodes, they will require new levels of power analysis performance and capacity improvements, as well as methods for mixing average currents (estimated or measured) with current waveforms and DC simulation results at the transistor, block, chip, or 3DIC level. The scalability and performance of the mPower platform provides Efinix with confidence knowing that, no matter what their designs may require in the future, they will continue to receive best-in-class, high-capacity EMIR analysis for their innovative FPGA designs.

For more details about Efinix and the mPower platform: Efinix implements effective EM/IR analysis for leading-edge FPGA designs with the mPower platform.

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