Power Is Now Every Engineer’s Concern

The pressure to ratchet down voltage has created problems in every part of the design flow.


Every semiconductor engineer by this point recognizes the need to reduce power inside of SoCs and software. What they don’t always see, though, is the chain of events those efforts are beginning to set off—unpredictable, difficult to model, and altogether more difficult to contain.

There is no doubt that more functionality on mobile devices requires new ways of designing SoCs, including revamping architectures, changing methodologies for when devices are turned on or off, how much computing is done per “on” cycle, how quickly to wake up certain blocks, how much area is relegated as dark silicon, and how low to drop the voltage. All of this is in the name of longer battery life and extending the time between charges.

What is less obvious are the side effects that each of these approaches has throughout the entire design cycle, from architecture to tapeout and even into field testing and longevity. This used to be the job of the power expert, and there is still a small band of engineers who fit this description. What’s changed is that it’s now everyone’s job to at least be aware that if voltage is turned down on one part of a chip, it may have effects in another. That could include everything from increased variability to timing issues, increased leakage current (heat), noise, and even electromagnetic interference.

There are a number other factors that need to be considered in this equation, as well:

  1. It’s much harder to verify the effects of power on functionality as you increase the number of techniques to improve energy efficiency. There are so many possible permutations that it’s mind-boggling, and even worse many of those permutations need to be measured over time because power effects change as devices are turned on and off at different rates.
  2. The more third-party IP that is included in a design, the harder it gets to track. The advantage of commercial IP is that it’s a black box. You don’t have to go in and fiddle with it. The disadvantage is that not all of it is characterized sufficiently to determine how it will be affected downstream from other blocks. In fact, it may be impossible to fully characterize IP with variable voltage rails all over an SoC, and IP vendors are reluctant to open their designs up too much because there’s proprietary knowledge inside.
  3. Turning on and off devices may make sense from a power standpoint, but ratcheting the power up and down also can have a variety of physical effects on those and nearby components, including wire fatigue and premature aging. These aren’t usually considerations in the smartphone world, but they’re very relevant in automotive infotainment systems.

And, of course, all of this creates pressure on market windows and development cost because it adds time and complexity to designs, even at established nodes using pre-existing subsystems and blocks. So while power may be the realm of power experts, it has now spilled over into everyone else’s world. Power was previously considered a global issue for a design. It has now become a global issue for everyone involved in that design, too.

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