Power/Performance Bits: Dec. 17

As academic and industry researchers search for new ways to continue on Moore’s Law, tunneling transistors and resistive random access memory are two potential technologies that could make it possible.

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Low-power tunneling transistor to enable high-performance devices
To make fast and low-power computing devices possible for energy-constrained applications such as smart sensor networks, implantable medical electronics and ultra-mobile computing, a new type of transistor is needed. To this end, researchers at Penn State, the National Institute of Standards and Technology and specialty wafer foundry IQE have developed what is called a near broken-gap tunnel field effect transistor (TFET) that uses the quantum mechanical tunneling of electrons through an ultrathin energy barrier to provide high current at low voltage.

According to the researchers, as device makers search for a way to continue shrinking the size of transistors and packing more transistors into a given area, TFET are considered to be a potential replacement for current CMOS transistors. The main challenge facing current chip technology is that as size decreases, the power required to operate transistors does not decrease in step. This impact can be seen in batteries that drain faster and heat dissipation that increases which can damage delicate electronic circuits. A number of new types of transistor architecture using materials other than the standard silicon are being studied to overcome the power consumption challenge.

The transistor was developed in the lab at Penn State to replace MOSFET transistors for logic applications and to address power issues. The team said it went a step beyond and showed the capability of operating at high frequency — handy for applications where power concerns are critical, such as processing and transmitting information from devices implanted inside the human body.

 Transmission electron microscope cross-section of the vertical TFET. The interface of the source and channel is the point where electron tunneling occurs. ILD is the interlayer dielectric separating the contacts. Top plane contacts are Gold (Au), Palladium (Pd), and Molybdenum (Mo). (Source: Penn State)

Transmission electron microscope cross-section of the vertical TFET. The interface of the source and channel is the point where electron tunneling occurs. ILD is the interlayer dielectric separating the contacts. Top plane contacts are Gold (Au), Palladium (Pd), and Molybdenum (Mo). (Source: Penn State)

For implanted devices, generating too much power and heat can damage the tissue that is being monitored, while draining the battery requires frequent replacement surgery. To account for this, the researchers tuned the material composition of the indium gallium arsenide/gallium arsenide antimony so that the energy barrier was close to zero — or near broken gap, which allowed electrons to tunnel through the barrier when desired. To improve amplification, the researchers said they moved all the contacts to the same plane at the top surface of the vertical transistor.

Mobile RRAM memory chip
With the potential to store more data using less space than the flash memory chips found in smart phones, tablets and laptops today, researchers at Stanford University have built a working prototype for a new type of memory chip.

The chips use resistive random access memory (RRAM) whereby resistance slows down electrons and conductivity lets electrons flow. By applying tiny jolts of voltage to carefully chosen materials, the Stanford engineers said they can toggle their RRAM chip between resistive and conductive states to create and store digital zeroes and ones.

Significantly, in addition to creating a working RRAM chip, the Stanford team has also shown how to fabricate these devices using processes that could be scaled up to produce these new memory chips in volume.

 

(Source: Stanford)

(Source: Stanford)

The researchers believe RRAM technology has potential beyond simply storing data. The principles behind RRAMs and the process used to make them could spawn an entirely new type of hybrid chip — one that would combine memory and microprocessor on a single slice of silicon.



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