Power/Performance Bits: July 28

Synthesizing graphene on silicon

Researchers from Korea University, in Seoul, developed an easy and microelectronics-compatible method to grow graphene and have successfully synthesized wafer-scale (four inches in diameter), high-quality, multi-layer graphene on silicon substrates. The method is based on an ion implantation technique, a process in which ions are accelerated under an electrical field and smashed into a semiconductor. The impacting ions change the physical, chemical or electrical properties of the semiconductor.

“For integrating graphene into advanced silicon microelectronics, large-area graphene free of wrinkles, tears and residues must be deposited on silicon wafers at low temperatures, which cannot be achieved with conventional graphene synthesis techniques as they often require high temperatures,” said Jihyun Kim, a professor in the Department of Chemical and Biological Engineering at Korea University. “Our work shows that the carbon ion implantation technique has great potential for the direct synthesis of wafer-scale graphene for integrated circuit technologies.”

“In silicon microelectronics, graphene is a potential contact electrode and an interconnection material linking semiconductor devices to form the desired electrical circuits,” said Kim. “This renders high processing temperature undesirable, as temperature-induced damage, strains, metal spiking and unintentional diffusion of dopants may occur.”

“The transferred graphene on the target substrate often contains cracks, wrinkles and contaminants,” said Kim. “Thus, we are motivated to develop a transfer-free method to directly synthesize high quality, multilayer graphene in silicon microelectronics.”

Wafer-scale synthesis of multi-layer graphene using high-temperature carbon ion implantation on nickel / SiO2 /silicon. (Source: J.Kim/Korea University)

Kim’s method relies on ion implantation, a microelectronics-compatible technique normally used to introduce impurities into semiconductors. In the process, carbon ions were accelerated under an electrical field and bombarded onto a layered surface made of nickel, silicon dioxide and silicon at the temperature of 500 degrees Celsius. The nickel layer, with high carbon solubility, is used as a catalyst for graphene synthesis. The process is then followed by high temperature activation annealing (about 600 to 900 degrees Celsius) to form a honeycomb lattice of carbon atoms, a typical microscopic structure of graphene.

The researchers’ next step is to further lower the temperature in the synthesis process and to control the thickness of the graphene for manufacturing production.

For phosphorene, use sticky tape

A team from the Australian National University created phosphorene by repeatedly using sticky tape to peel thinner and thinner layers of crystals from the black crystalline form of phosphorus.

As well as creating much thinner and lighter semiconductors than silicon, phosphorene has light emission properties that vary widely with the thickness of the layers, which enables much more flexibility for manufacturing.

“This property has never been reported before in any other material,” said Dr Lu, from ANU College of Engineering and Computer Science.

“By changing the number of layers we can tightly control the band gap, which determines the material’s properties, such as the color of LED it would make. You can see quite clearly under the microscope the different colors of the sample, which tells you how many layers are there,” said Dr Lu.

Dr Lu’s team found the optical gap for monolayer phosphorene was 1.75 electron volts, corresponding to red light of a wavelength of 700 nanometers. As more layers were added, the optical gap decreased. For instance, for five layers, the optical gap value was 0.8 electron volts, a infrared wavelength of 1550 nanometres. For very thick layers, the value was around 0.3 electron volts, a mid-infrared wavelength of around 3.5 microns.

The behavior of phosphorene in thin layers is superior to silicon, said Dr Lu.

Solar cells get boost from cookware

The same quality that buffers a raincoat against downpours or a pan against sticky foods can also boost the performance of solar cells, according to a new study from University of Nebraska-Lincoln engineers.

The study showed that constructing a type of organic solar cell on a “non-wetting” plastic surface made it 1.5 times more efficient at converting sunlight to electricity.

The researchers used the technique to grow polycrystalline cells, which are less expensive, faster and easier to produce than those made from only a single crystal. Yet single-crystal cells have traditionally boasted better efficiency, partly because they feature far fewer grains.

The team sought to reduce the number of these efficiency-draining barriers by increasing the size of the grains themselves. Though grain size is typically limited to the thickness of a solar cell, Huang’s team found that a non-wetting surface allowed it to fabricate grains up to eight times larger than the cell is thick.

As the name implies, a non-wetting surface causes liquid to bead and run off rather than spread and absorb on contact. The researchers discovered that this type of surface acted on grain boundaries in a similar fashion, accelerating their movement and encouraging the formation of larger grains when subjected to heat.

Using non-wetting surfaces as fabrication sites might also lead to improvements in other technology, the study reported, possibly in the form of faster transistors and more sensitive photodetectors.

“When it comes to electronic properties, crystallinity and grain size determine a lot,” said Jinsong Huang, associate professor of Mechanical and Materials Engineering at UNL. “So this is a simple method with a lot of potential applications.”