Proof of concept for a novel protection method, as an essential supplement to PERC in designs containing die-to-die IP.
All major foundries have adopted the programmable electrical rule checker (PERC) as the pre-silicon electrostatic discharge (ESD) signoff tool for IP and chip designs. This concept of rule checking works fine for most IP types, but for die-to-die IP, used in 3DIC designs, the PERC approach may not be appropriate. Die-to-die interface IP includes extremely large numbers of I/Os, trending towards hundreds of thousands of hybrid bonds in the near future, which are likely to surpass PERC capacity.
In addition, large I/O density requires optimal area-efficient ESD protection. Synopsys has introduced a novel form of ESD protection, in which active power clamps are abandoned. Instead, the clamping is realized by power decoupling capacitance, which enables power stabilization in normal operation and sufficient to meet the relatively low ESD targets valid for the internal die-to-die I/Os. The pre-silicon verification of a protection network based on distributed capacitance is beyond the scope of PERC and should be verified with a simulation-based tool.
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