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Precision Selective Etch And The Path To 3D

Selective isotropic etch is key to creating new gate-all-around structures.

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Scaling (the shrinking of the tiny devices in chips such as transistors and memory cells) has never been easy, but making the next generation of advanced logic and memory devices a reality requires creating new structures at the atomic scale. When working with dimensions this small, there is little room for variation.

Compounding the problem is a need to remove material isotropically, or, uniformly in all directions. As device architectures change in pursuit of higher performance chips, new processes are needed. In gate-all-around (GAA) structures, for example, sacrificial silicon germanium (SiGe) layers will need to be either partially or fully removed by isotropic etching, with no loss or damage to the neighboring silicon layers.

Transition from finFET to GAA drives critical isotropic selective etch requirements. 

Precision selective etch and surface treatment

Precision selective etch is best visualized in the four-material example shown in the figures below, where typical requirements are to etch the material shown in green by a precise amount and at a controlled isotropic profile angle – without etching or damaging any of the other layers.

Precision surface treatment requires a material property modification of one layer to improve device performance without damaging or modifying the other layers.

New materials require precision energy tuning

When creating today’s device structures, a common processing step involves removing silicon (Si) while leaving a silicon oxide (SiO2) layer behind. In an ion based etch, we control what film is removed using masks which protect the layers that should not be removed.

With our selective etch products, we can selectively remove only silicon and leave behind the silicon oxide by creating an exceptionally low energy flux of etchants with energies greater than the Si-Si bonding energy (3.4 eV), but less than the silicon and oxygen (Si-O) bonding energy (8.3 eV) – a relatively small range of 4.9 eV.

New materials, however, have a dramatically smaller range. For example, removing only SiGe layers and not adjacent Si layers in a GAA device requires energy turning in a range of less than 0.3 eV.

Truly precise selective etch requires advanced high-resolution energy tuning as a fundamental part of the system design. This capability far exceeds the performance levels supported by conventional “bulk” etch approaches. Moreover, it requires a complex combination of added steps, processes, and chambers to meet the exacting requirements for atomic-layer accuracy, which is at the heart of Lam’s selective etch product designs.

New materials driving the need for high-resolution energy tuning.

Taking selective etch to the next level

Lam’s new suite of precision selective etch tools and surface treatments are poised to accelerate chipmakers’ 3D logic and memory roadmaps – a major evolutionary leap forward for the semiconductor industry.

  • Argos provides a new selective surface treatment. The innovative element in the Argos system is MARS (metastable active radical source), which creates the very gentle radical plasma necessary for highly selective surface property modification needed in advanced logic applications.
  • Prevos employs a chemical vapor reactor for extremely low energy, high precision selective etch. A new, proprietary chemistry catalyst has been developed specifically for the extreme high selectivity requirements of applications such as native oxide breakthrough, precision trim and recess.
  • Selis takes energy tuning to a whole new level by controlling plasma with a low-energy radical source. It also has an extremely low energy processing mode designed for the most extreme applications where selectivity must be ultra-high, such as with the critical SiGe selective etch steps used to form GAA structures. The process is so precise that Selis can etch SiGe layers without damaging or roughening the critical Si layers.

Greater innovation through collaboration

Supporting our customers’ 3D roadmaps has required bold new developments in source technology, chemistries, materials science, and other radical chamber hardware designs. I am enormously proud of the team we assembled at Lam to make these products a reality, which included some our top technologists focused on developing source technology and game-changing chamber hardware designs, and an amazing group of chemists focused on developing novel chemistries to support our innovative approach to etch processes and surface treatments. Working collaboratively with our customers and across technical specialties and product groups, they have produced selective etch innovation that will make it possible for the world’s leading chipmakers to deliver the 3D logic and memory devices of the future.



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