Preparing For Change

Throw out the most optimistic and the most pessimistic predictions about the future of the foundry model and you probably arrive at a reasonable approximation of how things will actually play out.

It’s clear that the number of customers at the front end of process technology will shrink after 20nm. It simply costs too much to design and manufacture a chip, and there aren’t enough markets capable of offering sufficient return on investment. The trend is toward smaller, fragmented markets, not one or two megamarkets. It’s also likely that the amount of money that needs to be invested in fabs after 20nm for planar SoCs may never be fully recouped, which explains Intel’s recent spate of investments in other companies.

That doesn’t mean there won’t be progress in either manufacturing or design, however, and it doesn’t mean there won’t be a need for lots of very expensive equipment. The next step is stacking of die, which already is under way. The semi industry is likely to do a double hop to 3D-ICs, with 2.5D being a commercially viable step in the short term and volume production in real 3D sometime in the second half of the decade. Exact timing depends on a number of factors, including progress in lithography, maturation of TSVs, the ability to control leakage and deal with heat caused by that leakage, and ecosystem standards that prevent a lot of finger-pointing when something does go wrong.

This represents an enormous opportunity for both manufacturing and design, rather than a reduction in new opportunities. Being able to accurately place TSVs on a substrate, to fuse together various die properly, to thin them to exact measurements—nanometers rather than millimeters—and to test them is every bit as complex as building planar devices. But it also provides a huge degree of freedom to chipmakers because it allows them to use whatever process node makes sense for a particular part of an SoC.

Still, it does raise the specter of competition from other sectors. The stakes are high and this is an inflection point. While it’s doubtful there will be a huge change on the equipment side, because of the cost of developing new equipment is enormous, it’s almost inevitable that there will be a scramble on the manufacturing side. The foundries have already offered a peak of their strategy by jealously safeguarding the interposer technology they have developed, and OSATs are scrambling to do the bonding and testing for stacked die.

IDMs are likely to get involved, as well. Intel has created a commercial foundry operation, and Samsung has been offering foundry services to large customers for some time. It’s too expensive to run their fabs partially full, as they did in the past, and they need customers to help bear the costs. Those costs will likely increase as 3D stacking gets rolling, although the amortization of those costs likely will be dragged out because a 22nm process may get fused together with a chip that was made with 14nm process technology and another one—perhaps an analog sensor, for example—at a new, low-power 130nm process.

The biggest question marks are in lithography. Does the industry move to multipatterning, commercially available EUV, directed self-assembly, or some combination of all of the above, with e-beam and gridded design rules thrown in for good measure. The future will be some combination of all of the above, shaving costs wherever it makes sense and adding them in other places where volume and efficiency can be justified.

This is hardly a scenario for doom and gloom, but it isn’t necessarily a step up for everyone involved in the supply chain. The real question isn’t whether the foundry model is doomed and whether equipment spending is over. It’s who will reap the biggest benefits from these shifts and be able to call the shots in the supply chain. So far that isn’t clear, but the posturing and positioning is already beginning.