Preparing For 3D IC Stacking

Through-silicon vias getting closer to prime time; tools begin rolling out for manufacturing 3D chips.


By David Lammers
Through-silicon vias (TSVs) are in various stages of late development, but design and manufacturing challenges remain before companies can gain the full benefits of the third dimension.

Two camps are pushing hard to introduce TSVs—the design community and the manufacturing equipment companies. The initial goal is to connect graphics memories to graphics processors in mobile systems. Integrated device manufacturers (IDMs) such as Samsung Electronics are racing to use TSVs to couple high-bandwidth DRAMs with processors. Samsung counts Apple as a major customer. Qualcomm and foundry partner TSMC are creating their own design and manufacturing ecosystem for TSV-enhanced mobile IC solutions.

Sesh Ramaswami, senior director of strategy for the TSV program at Applied Materials said Applied has had about 50 people working on TSV-related technologies since 2008, and now has a complete toolset ready. “We are extending all of the knowledge gained from Damascene processing (for copper chip interconnects) to TSVs,” he said.

The equipment and materials companies have gained valuable learning from the early adoption of TSVs in CMOS image sensors, said Didier Louis, a project leader at the Leti R&D consortium in Grenoble, France. Leti worked closely with STMicroelectronics and Nokia to develop a TSV process flow, used to create image sensors in which the TSVs connect the CMOS image sensor and memory. Leti is not yet working on a logic-to-memory TSV solution, but Louis said, “We have in our toolbox all the knowledge. To manage a logic-memory TSV integration it helps if the dice are the same size, and if the manufacturer knows where to drill the vias.”

Signal and ground TSV architectures may be needed for video applications. (Source: Robert Geer, CSNSE)

Fig. 1: Signal and ground TSV architectures may be needed for video applications. (Source: Robert Geer, CSNSE)

Getting the bandwidth increases promised by TSVs will require careful interconnect design optimization, said Robert Geer, a professor at the College of Nanoscale Science and Engineering in Albany, N.Y.. “Every time a designer uses a TSV, you are losing device area,” Geer said, noting that about 10% of the typical die area is consumed by the vertical interconnects. While performance gains are there to be had, Geer reminded an audience at Semicon West that “as nice as TSVs are, they are still copper, which has a frequency limit of about 1GHz” for a 5µm-diameter TSV. For memory access, bandwidth of 2 terabits per second (Tb/s) is sufficient, but logic-to-logic computation requires 5 to 6 Tb/s, and RF signals need much more bandwidth, 50 to 100 Tb/s.

Video and RF will require up to 100 Tb/s of bandwidth. (Source: Robert Geer, CNSE)

Fig. 2: Video and RF will require up to 100 Tb/s of bandwidth. (Source: Robert Geer, CNSE)

Power is a critical issue. “You want the signals to go through (from logic to memory) at a femtoJoule rate,” Geer said.

For power-conscious mobile systems, TSVs are the only realistic way to connect a graphics/video processor to several layers of graphics memory, where 12.8 GB/s of bandwidth is needed between the processor and DRAM memory for high-definition video. A conventional (non-TSV) HD video solution would require high-frequency operation over 2,000 I/O pins, a non-starter for any battery-operated system, said Pol Marchal, director of IMEC’s TSV development effort.

Geer and CNSE colleague Wei Wang have studied the interconnect architectures needed for “many-core” SoCs with the processor blocks running at relatively low frequencies. Network-on-chip (NoC) architectures for these TSV-enhanced many-core solutions will be required. For video processing and other high-bandwidth requirements, Geer said a coaxial interconnect design, with each signal TSV surrounded by four ground/buffer TSVs, may be required.

While the design community develops the expertise and EDA tools required for TSV-enhanced interconnect architectures, the equipment and materials vendors are ironing out their own challenges. Fusen Chen, executive vice president at Novellus Systems, said TSVs of 5 to 6µm are difficult to fill without voids. Because of the CTE mismatch between copper and silicon, “the copper wants to pump out” from the via, Chen said, adding that for Novellus “the key is our ability to pre-wet in a unique way.”

Keeping the cost of electroplating down, particularly for high-aspect ratio (20:1) vias, is another challenge, Chen said. Novellus introduced its Sabre 3D electroplating system, optimized for TSVs, redistribution layers (RDLs), and other wafer-level packaging applications at Semicon West this month. That sets the stage for an intense electroplating competition between Novellus and Applied Materials, which last year bought electoplating vendor Semitool Inc. (Kalispell, Mont.).

Also at Semicon West, Applied introduced the Avila CVD system for the vias-last TSV process flow, where temperature control is critical. In the vias-last flow, TSVs are formed from the backside after the wafer is thinned. In the vias-middle approach, the TSVs are created in the wafer fab after formation of the contacts.

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