Meeting the pressures of increased cost per transistor below 28nm won’t be easy, but memory compiler IP technology holds promise.
The scaling benefits of are being seriously tested at 28nm. It is no longer a given that the cost per gate will go down at leading edge process nodes below 28nm, e.g., 20nm though 14nm. Rising design and manufacturing costs are contributing factors to this trend.
Meanwhile, the competing trend of fewer but more complex (SoC) designs is reducing the knowledge base of many chip design teams. The reduction in knowledge means less availability at leading-edge process nodes. What can be done to mitigate these challenging trends?
Embedded memory continues to dominate the die area of many chips regardless of the process node. This suggests that significant benefit can be achieved by customizing the memory architectures of an SoC early on in the design process as part of the overall SoC optimization for power, performance and die area.
This white paper explores these challenges and highlights custom IP memory optimization strategies as a solution at leading-edge nodes. To read more, click here.
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