Challenges In Using HLS For FPGA Design

High-level synthesis (HLS) tools, which transform C/C++ source code to Verilog/VHDL, have been commercially available for over 15 years. HLS tools from FPGA vendors and EDA companies promise improved productivity through a higher-level of abstraction, faster verification and quicker design iterations. For example, simulating your design in C/C++ can be 10 to 100x faster than simulating in RTL (... » read more

Tech Talk: TCAM

Dennis Dudeck, IP solutions FAE at eSilicon, talks about how to save power and area with ternary content addressable memory. » read more

Quantifying IP Entitlement For 14/16nm Technologies

The scaling benefits of [getkc id="74" comment="Moore"s Law"] are being seriously tested at 28nm. It is no longer a given that the cost per gate will go down at leading edge process nodes below 28nm, e.g., 20nm though 14nm. Rising design and manufacturing costs are contributing factors to this trend. Meanwhile, the competing trend of fewer but more complex [getkc id="81" comment="SoC"] (So... » read more