Reduce Verification Complexity In Low/Multi-Power Designs

How to cut cost and time to market while improving yield and reliability.

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Accurate and efficient low-power and multiple-power domain verification requires both knowledge of the overall system’s power intent and careful tracking of signals crossing these power domains. Calibre PERC is the only comprehensive solution capable of providing transistor-level power intent verification without the need for SPICE simulation on both the schematic and layout side of your design. As part of the Calibre platform, it integrates easily into existing signoff flows, with comprehensive debugging support provided by Calibre RVE. Calibre PERC provides an easy-to-use, automated verification solution for low-power and multiple-power domain designs, ultimately reducing cost and time to market, while providing the diagnostic insight to help you improve yield and device reliability.

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