Prediction of SRAM Reliability Under Mechanical Stress Induced by Harsh Environments


On the example of a 28nm SRAM array, this work presents a novel reliability study which takes into account the effect of externally applied mechanical stress in circuit simulations. This method is able to predict the bit failures caused by the stress via the piezoresistive effect. The stability of each single SRAM cell is simulated using static noise margin. Finally, the whole array’s behavio... » read more

New Thermal Issues Emerge


Thermal monitoring is becoming more critical as gate density continues to increase at each new node and as chips are developed for safety critical markets such as automotive. This may sound counterintuitive because the whole point of device scaling is to increase gate density. But at 10/7 and 7/5nm, static current leakage is becoming a bigger issue, raising questions about how long [getkc id... » read more

Reduce Verification Complexity In Low/Multi-Power Designs


Accurate and efficient low-power and multiple-power domain verification requires both knowledge of the overall system’s power intent and careful tracking of signals crossing these power domains. Calibre PERC is the only comprehensive solution capable of providing transistor-level power intent verification without the need for SPICE simulation on both the schematic and layout side of your desi... » read more

Mixed-Signal Design Powers Ahead


Mixed-signal devices are at the heart of many advanced systems today because of the need to interact with the outside world, but designing and verifying these systems is getting harder. There are several reasons for this. First, almost all of these devices now have to be lower power than in the past, and in the analog space it's not as simple as just dialing down part of a block. Second, it ... » read more