Reducing The Drama In DFM

Pattern-matching technology finds its place in the silicon design ecosystem as complexity and yield issues grow.

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By Ann Steffora Mutschler
For reducing cycle time of DFM checks prior to manufacturing, pattern matching is a topic of great excitement as of the past few manufacturing nodes.

The idea behind the technology is that there are certain patterns in the physical layout of the chip, which unless they are addressed, won’t come out right. That’s what causes the drama, observed Saleem Haider, senior director of marketing for physical design and DFM at Synopsys. “The way we used to do things is not going to work anymore.”

It’s common knowledge that getting a good yield at advanced nodes is getting tougher. “It’s a big challenge for foundries because the lithography equipment is still the same and they are pushing the technology nodes,” said Manoj Chacko, product marketing director at Cadence. “At 28nm they are using the 193nm immersion stepper or scanner. At 20nm it is the same equipment; at 16nm it’s probably going to be the same machine and most likely for 10nm it is likely to be the same machine unless EUV kicks off. What’s happening here happening here is that the wavelength is 193nm, immersion has to improve the K-1 factor, but the foundries are pushing feature sizes more than 10 times smaller. So the lithography issue is a big problem.”

Finding lithography issues in a design is based on computational lithography, which is an extremely compute-intensive process. “Compute-intensive processes are good in manufacturing and were okay at 40nm, but as we go down to 28nm and 20nm the computing power needed is not like just 1X or 2X. It’s almost like 5X or 10X more, so the number of CPUs needed to do a job is higher,” Chacko pointed out.

While a fab or foundry may be outfitted with the CPU power to handle these processes, the design team is not. This is where is where pattern analysis comes in. “Just like the same thing we are hearing in the Web space— they call it big data—there is a similar analogy here. How do you process large amounts of data in an intelligent way? That is the whole crux of this thing.”

Cadence, Mentor Graphics and Synopsys all have worked with the foundries on essential pattern matching meant to evolve DFM signoff with minimal impact to the design community. Each has its own approach, but they all meet the requirement of the foundry for signoff.

In the case of Cadence, following the acquisition of CommandCAD in 2007, the company includes pattern classification as the core essence of its approach in order to reduce the sheer number of patterns from the foundry, which could number in the hundreds of thousands depending on the process.

“What we do for foundries with this technology for pattern classification is to try and reduce hundreds of thousands of patterns into pattern families. If we can reduce say 100,000 patterns into 100 patterns, this becomes an economical and deployable capability for the design community. We are able to reduce and classify hundreds of thousands of patterns into pattern families. So what pattern matching tools do is they have the tech file, which is a library of about patterns from the foundry, and after they’ve done routing they do a pattern certain match. Whatever that patterns are found that information is fed back to the router to avoid those patterns,” Chacko said.

In the case of lithography hotspot checking, which also falls into the pattern-matching genre, it turns out that there are certain specific patterns and combinations of physical shape. When one shape of a certain type is next to another shape of this type and it is exposed to lithography, it will not come out right. There may be some pinching or shorts– and those patterns need to be fixed, Haider explained.

“The set of patterns that are bad—the violating patterns—for a given node is not necessarily a static set. So we start with a large number of potential violators. As the process matures the people in the factory fine-tune the processes and the patterns are not violators anymore, so slowly the need for very strict checking gets mitigated. This is what we saw at 45nm. We are seeing a bit of it at 28nm as well, and at 20nm it remains to be seen,” he continued.

Identifying and preventing problems
At Synopsys, Haider noted that the company has been working on hotspot checking technology for a long time and has invested in internal development. The company comes at the problem from two trajectories.

First is the ability to perform a detailed lithography simulation on the entire design whereby it is very exact but admittedly heavy. There is also a pattern matching technology where instead of simulating the entire process Synopsys works with the
foundry to obtain a library of potentially offending patterns, searches the design for those, and that is 1,000 times faster than the first approach.

Technically, explained Stelios Diamantidis, product marketing manager at Synopsys, “with pattern matching technology what we’re doing is taking a problem that is very mathematical on the foundry side—it is very much related to optics and simulation and applies a lot of high complexity convolution to design shapes—and we are turning it into a much more manageable physical design and verification problem that is closer to a traditional design rule check or a search-and-repair type application. That’s really the special sauce in the pattern matching technology—how to transition from a foundry-side manufacturing application into something that can be much more designer friendly and also much more intuitive and usable. The technology itself really works with managing geometries. It leverages our hierarchical design analysis validator, which we use for design rule checks, but then translates this or augments it into a two-dimensional space, multi-shape search capability.”

Michael White, director of product marketing for Calibre physical verification at Mentor Graphics, agreed that the challenge that engineers have seen is that doing simulation over the entire design is very computationally expensive and the run times for doing lithography at the full chip level are prohibitively long. “Lots of folks were doing full litho on their IP. They were doing full litho on their IP blocks as they were building up their design. But when they were getting to the full chip level the pain level was pretty high. That is still true today where folks are doing full LFD simulation at the cell or block level as they are building up their design. But again, you need to come up with a different strategy at the full-chip level.”

That is why pattern matching has become so interesting at 28nm as the way to make it practical to do full-chip lithography simulation. Using the equation-based DRC technology, he noted that when a match is found, the designer can get a hint on how to fix the problem within the flow.

Interestingly, White has observed more rapid adoption by fabless companies because while producing a new chip, “they get back that their yields aren’t quite what they want. Their failure analysis teams working at the last chip [tell them], ‘We had a failure here, we had a failure there.’ The failure analysis team typically are former foundry or fab folks, so they are used to looking at a CD SEM and looking a series of shapes. The traditional communication methodology was for them to draw on a piece of paper and say, ‘I saw this set of shapes.’ Somebody then tries to use a text-based syntax to describe that, and then they go off and do checks to find out if there are other designs in process within the company, and whether this pattern is present anywhere else. That whole flow takes weeks, and you are going from a CD SEM image, to something on paper, to a text-based syntax. You are transforming how you are communicating what the problem is through multiple different mediums. It’s not very effective.”

Pattern matching allows the DFM engineers to clip out patterns from the GDS and use that to populate a library of weak and detractor patterns, which significantly speeds up the feedback loop from what they were finding in failure analysis and test back up to the design teams. That allows the teams to start fixing yield detractor patterns and stop using the patterns that cause problems, he said.