Memory: Programmable photonic latch; gradient computing with memristors; writing MRAM.
Researchers from Nokia Bell Labs developed a new type of optical memory called a programmable photonic latch that enables temporary data storage in optical processing systems. It is modeled after a set-reset latch.
The integrated programmable photonic latch is based on optical universal logic gates using silicon photonic micro-ring modulators and can be implemented in commercially available silicon photonic chip fabrication processes. Demonstrated using a programmable silicon photonic platform, the photonic latch offers features such as optical set and reset, complementary outputs, scalability and compatibility with wavelength division multiplexing (WDM).
“Because each memory unit has an independent input light source, it is possible to have several memory units working independently without affecting each other through optical power loss propagation,” said Farshid Ashtiani from Nokia Bell Labs, in a press release. “The memory units can also be co-designed with the existing silicon photonic systems and be built reliably and with very high yields.” [1]
Researchers from the University of California Santa Barbara, Hewlett Packard Labs, and Aachen University developed specialized function gradient computing hardware to accelerate the solving of complex high-order optimization problems.
“The objective function of any optimization problem, such as an AI workload, represents an N-dimensional ‘energy landscape,’ where each combination of variable values represents a unique point in that landscape. The goal is to find the set of variable assignments that corresponds to the lowest — or more generally, as close as possible to the lowest — point in that landscape,” said Tinish Bhattacharya, a doctoral student at UC Santa Barbara, in a statement. “The gradient calculation operation is performed iteratively, over and over, and we need to be able to do it fast and efficiently.”
The in-memory compute hardware, made up of crossbar arrays of specialized memristor devices, can perform matrix vector multiplication to solve problems like Boolean Satisfiability in their native high-order space without having to do any pre-processing, providing a speedup over hardware architectures that are limited to second-order objective functions.
“The hardware consists of crossbar memories — actual raised surfaces lithographed onto the chip — where several word lines (wires) run horizontally and several bit lines run vertically. Placing a memristor at every location where a word line and a bit line intersect, with one terminal of the device connected to the word line and the other to the bit line, forms a memristor crossbar array. The matrix encoding the problem is stored in the states of these memristors. The vector is applied as proportional read pulses on the word lines. The resulting currents, which flow in the bit lines, then depict the result of the vector-matrix multiplication,” explained UC Santa Barbara’s James Badham, in a release. “The core innovation that enables gradient computation of high-order polynomials in the native (high-order) space is using two such crossbar arrays back to back. Both crossbars store the matrix depicting the high-order polynomial. The first crossbar computes the high-order monomials of the polynomial. The second crossbar uses this result as its input to compute the high-order gradient for all the variables in each of its bit lines.” [2]
Researchers from Osaka University proposed an electric-field-based writing scheme as a way to lower the power consumption of MRAM.
The new MRAM component uses a multiferroic heterostructure with magnetization vectors that can be switched by an electric field. To make it more stable, they inserted an ultra-thin vanadium layer between the ferromagnetic and piezoelectric layers. The device showed a high converse magnetoelectric (CME) coupling coefficient, indicating strong magnetization response.
The researchers were able to realize two different magnetic states at zero electric field by changing the sweeping operation of the electric field, enabling a non-volatile binary state to be intentionally achieved at zero electric field.
“Through precise control of the multiferroic heterostructures, two key requirements for implementing practical magnetoelectric (ME)-MRAM devices are satisfied, namely a non-volatile binary state with zero electric field, and a giant CME effect,” said Kohei Hamaya, a professor at Osaka University, in a statement. The researchers believe the approach could eventually be implemented on practical MRAM devices. [3]
[1] Ashtiani, F. Programmable photonic latch memory. Opt. Express 33, 3501-3510 (2025) https://doi.org/10.1364/OE.536535
[2] Bhattacharya, T., Hutchinson, G.H., Pedretti, G. et al. Computing high-degree polynomial gradients in memory. Nat Commun 15, 8211 (2024). https://doi.org/10.1038/s41467-024-52488-y
[3] Usami, T., Sanada, Y., Fujii, S. et al. Artificial Control of Giant Converse Magnetoelectric Effect in Spintronic Multiferroic Heterostructure. Adv. Sci. 2024, 2413566. https://doi.org/10.1002/advs.202413566
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